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Documentation / arm / Samsung-S3C24XX / DMA.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 08:59 EST.

1				S3C2410 DMA
2				===========
3	
4	Introduction
5	------------
6	
7	   The kernel provides an interface to manage DMA transfers
8	   using the DMA channels in the CPU, so that the central
9	   duty of managing channel mappings, and programming the
10	   channel generators is in one place.
11	
12	
13	DMA Channel Ordering
14	--------------------
15	
16	   Many of the range do not have connections for the DMA
17	   channels to all sources, which means that some devices
18	   have a restricted number of channels that can be used.
19	
20	   To allow flexibility for each CPU type and board, the
21	   DMA code can be given a DMA ordering structure which
22	   allows the order of channel search to be specified, as
23	   well as allowing the prohibition of certain claims.
24	
25	   struct s3c24xx_dma_order has a list of channels, and
26	   each channel within has a slot for a list of DMA
27	   channel numbers. The slots are searched in order for
28	   the presence of a DMA channel number with DMA_CH_VALID
29	   or-ed in.
30	
31	   If the order has the flag DMA_CH_NEVER set, then after
32	   checking the channel list, the system will return no
33	   found channel, thus denying the request.
34	
35	   A board support file can call s3c24xx_dma_order_set()
36	   to register a complete ordering set. The routine will
37	   copy the data, so the original can be discarded with
38	   __initdata.
39	
40	
41	Authour
42	-------
43	
44	Ben Dooks,
45	Copyright (c) 2007 Ben Dooks, Simtec Electronics
46	Licensed under the GPL v2
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