Based on kernel version 2.6.38. Page generated on 2011-03-22 22:18 EST.
1 README on the IOBARRIER for CardEngine IO 2 ========================================= 3 4 Due to an unfortunate oversight when the Card Engines were designed, 5 the signals that control access to some peripherals, most notably the 6 SMC91C9111 ethernet controller, are not properly handled. 7 8 The symptom is that some back to back IO with the peripheral returns 9 unreliable data. With the SMC chip, you'll see errors about the bank 10 register being 'screwed'. 11 12 The cause is that the AEN signal to the SMC chip does not transition 13 for every memory access. It is driven through the CPLD from the CS7 14 line of the CPU's static memory controller which is optimized to 15 eliminate unnecessary transitions. Yet, the SMC requires a transition 16 for every write access. The Sharp website has more information about 17 the effect this power-conserving feature has on peripheral 18 interfacing. 19 20 The solution is to follow every write access to the SMC chip with an 21 access to another memory region that will force the CPU to release the 22 chip select line. It is important to guarantee that this access 23 forces the CPU off-chip. We map a page of SDRAM as if it were an 24 uncacheable IO device and read from it after every SMC IO write 25 operation. 26 27 SMC IO 28 BARRIER IO 29 30 Only this sequence is important. It does not matter that there is no 31 BARRIER IO before the access to the SMC chip because the AEN latch 32 only needs occurs after the SMC IO write cycle. The routines that 33 implement this work-around make an additional concession which is to 34 disable interrupts during the IO sequence. Other hardware devices 35 (the LogicPD CPLD) have registers in the same physical memory 36 region as the SMC chip. An interrupt might allow an access to one of 37 those registers while SMC IO is being performed. 38 39 You might be tempted to think that we have to access another device 40 attached to the static memory controller, but the empirical evidence 41 indicates that this is not so. Mapping 0x00000000 (flash) and 42 0xc0000000 (SDRAM) appear to have the same effect. Using SDRAM seems 43 to be faster. Choosing to access an undecoded memory region is not 44 desirable as there is no way to know how that chip select will be used 45 in the future.