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Based on kernel version 3.15.4. Page generated on 2014-07-07 08:59 EST.

1	                 MFP Configuration for PXA2xx/PXA3xx Processors
2	
3				Eric Miao <eric.miao@marvell.com>
4	
5	MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
6	later PXA series processors.  This document describes the existing MFP API,
7	and how board/platform driver authors could make use of it.
8	
9	 Basic Concept
10	===============
11	
12	Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
13	mechanism is introduced from PXA3xx to completely move the pin-mux functions
14	out of the GPIO controller. In addition to pin-mux configurations, the MFP
15	also controls the low power state, driving strength, pull-up/down and event
16	detection of each pin.  Below is a diagram of internal connections between
17	the MFP logic and the remaining SoC peripherals:
18	
19	 +--------+
20	 |        |--(GPIO19)--+
21	 |  GPIO  |            |
22	 |        |--(GPIO...) |
23	 +--------+            |
24	                       |       +---------+
25	 +--------+            +------>|         |
26	 |  PWM2  |--(PWM_OUT)-------->|   MFP   |
27	 +--------+            +------>|         |-------> to external PAD
28	                       | +---->|         |
29	 +--------+            | | +-->|         |
30	 |  SSP2  |---(TXD)----+ | |   +---------+
31	 +--------+              | |
32	                         | |
33	 +--------+              | |
34	 | Keypad |--(MKOUT4)----+ |
35	 +--------+                |
36	                           |
37	 +--------+                |
38	 |  UART2 |---(TXD)--------+
39	 +--------+
40	
41	NOTE: the external pad is named as MFP_PIN_GPIO19, it doesn't necessarily
42	mean it's dedicated for GPIO19, only as a hint that internally this pin
43	can be routed from GPIO19 of the GPIO controller.
44	
45	To better understand the change from PXA25x/PXA27x GPIO alternate function
46	to this new MFP mechanism, here are several key points:
47	
48	  1. GPIO controller on PXA3xx is now a dedicated controller, same as other
49	     internal controllers like PWM, SSP and UART, with 128 internal signals
50	     which can be routed to external through one or more MFPs (e.g. GPIO<0>
51	     can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
52	     see arch/arm/mach-pxa/mach/include/mfp-pxa300.h)
53	
54	  2. Alternate function configuration is removed from this GPIO controller,
55	     the remaining functions are pure GPIO-specific, i.e.
56	
57	       - GPIO signal level control
58	       - GPIO direction control
59	       - GPIO level change detection
60	
61	  3. Low power state for each pin is now controlled by MFP, this means the
62	     PGSRx registers on PXA2xx are now useless on PXA3xx
63	
64	  4. Wakeup detection is now controlled by MFP, PWER does not control the
65	     wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
66	     (as defined in pxa3xx-regs.h) controls the wakeup from MFP
67	
68	NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
69	mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
70	pad (or ball).
71	
72	 MFP API Usage
73	===============
74	
75	For board code writers, here are some guidelines:
76	
77	1. include ONE of the following header files in your <board>.c:
78	
79	   - #include <mach/mfp-pxa25x.h>
80	   - #include <mach/mfp-pxa27x.h>
81	   - #include <mach/mfp-pxa300.h>
82	   - #include <mach/mfp-pxa320.h>
83	   - #include <mach/mfp-pxa930.h>
84	
85	   NOTE: only one file in your <board>.c, depending on the processors used,
86	   because pin configuration definitions may conflict in these file (i.e.
87	   same name, different meaning and settings on different processors). E.g.
88	   for zylonite platform, which support both PXA300/PXA310 and PXA320, two
89	   separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c
90	   (in addition to handle MFP configuration differences, they also handle
91	   the other differences between the two combinations).
92	
93	   NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
94	   PXA310 supporting some additional ones), thus the difference is actually
95	   covered in a single mfp-pxa300.h.
96	
97	2. prepare an array for the initial pin configurations, e.g.:
98	
99	   static unsigned long mainstone_pin_config[] __initdata = {
100		/* Chip Select */
101		GPIO15_nCS_1,
102	
103		/* LCD - 16bpp Active TFT */
104		GPIOxx_TFT_LCD_16BPP,
105		GPIO16_PWM0_OUT,	/* Backlight */
106	
107		/* MMC */
108		GPIO32_MMC_CLK,
109		GPIO112_MMC_CMD,
110		GPIO92_MMC_DAT_0,
111		GPIO109_MMC_DAT_1,
112		GPIO110_MMC_DAT_2,
113		GPIO111_MMC_DAT_3,
114	
115		...
116	
117		/* GPIO */
118		GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
119	   };
120	
121	   a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
122	   and written to the actual registers, they are useless and may discard,
123	   adding '__initdata' will help save some additional bytes here.
124	
125	   b) when there is only one possible pin configurations for a component,
126	   some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on
127	   PXA25x and PXA27x processors
128	
129	   c) if by board design, a pin can be configured to wake up the system
130	   from low power state, it can be 'OR'ed with any of:
131	
132	      WAKEUP_ON_EDGE_BOTH
133	      WAKEUP_ON_EDGE_RISE
134	      WAKEUP_ON_EDGE_FALL
135	      WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,
136	
137	   to indicate that this pin has the capability of wake-up the system,
138	   and on which edge(s). This, however, doesn't necessarily mean the
139	   pin _will_ wakeup the system, it will only when set_irq_wake() is
140	   invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq())
141	   and eventually calls gpio_set_wake() for the actual register setting.
142	
143	   d) although PXA3xx MFP supports edge detection on each pin, the
144	   internal logic will only wakeup the system when those specific bits
145	   in ADxER registers are set, which can be well mapped to the
146	   corresponding peripheral, thus set_irq_wake() can be called with 
147	   the peripheral IRQ to enable the wakeup.
148	
149	
150	 MFP on PXA3xx
151	===============
152	
153	Every external I/O pad on PXA3xx (excluding those for special purpose) has
154	one MFP logic associated, and is controlled by one MFP register (MFPR).
155	
156	The MFPR has the following bit definitions (for PXA300/PXA310/PXA320):
157	
158	 31                        16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
159	  +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
160	  |         RESERVED        |PS|PU|PD|  DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL |
161	  +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
162	
163	  Bit 3:   RESERVED
164	  Bit 4:   EDGE_RISE_EN - enable detection of rising edge on this pin
165	  Bit 5:   EDGE_FALL_EN - enable detection of falling edge on this pin
166	  Bit 6:   EDGE_CLEAR   - disable edge detection on this pin
167	  Bit 7:   SLEEP_OE_N   - enable outputs during low power modes
168	  Bit 8:   SLEEP_DATA   - output data on the pin during low power modes
169	  Bit 9:   SLEEP_SEL    - selection control for low power modes signals
170	  Bit 13:  PULLDOWN_EN  - enable the internal pull-down resistor on this pin
171	  Bit 14:  PULLUP_EN    - enable the internal pull-up resistor on this pin
172	  Bit 15:  PULL_SEL     - pull state controlled by selected alternate function
173	                          (0) or by PULL{UP,DOWN}_EN bits (1)
174	
175	  Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
176	  Bit 10-12: DRIVE  - drive strength and slew rate
177				0b000 - fast 1mA
178				0b001 - fast 2mA
179				0b002 - fast 3mA
180				0b003 - fast 4mA
181				0b004 - slow 6mA
182				0b005 - fast 6mA
183				0b006 - slow 10mA
184				0b007 - fast 10mA
185	
186	 MFP Design for PXA2xx/PXA3xx
187	==============================
188	
189	Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
190	MFP API is introduced to cover both series of processors.
191	
192	The basic idea of this design is to introduce definitions for all possible pin
193	configurations, these definitions are processor and platform independent, and
194	the actual API invoked to convert these definitions into register settings and
195	make them effective there-after.
196	
197	  Files Involved
198	  --------------
199	
200	  - arch/arm/mach-pxa/include/mach/mfp.h
201	  
202	  for
203	    1. Unified pin definitions - enum constants for all configurable pins
204	    2. processor-neutral bit definitions for a possible MFP configuration
205	
206	  - arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
207	
208	  for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
209	  configurations
210	
211	  - arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
212	
213	  for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations
214	
215	  - arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
216	    arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
217	    arch/arm/mach-pxa/include/mach/mfp-pxa300.h
218	    arch/arm/mach-pxa/include/mach/mfp-pxa320.h
219	    arch/arm/mach-pxa/include/mach/mfp-pxa930.h
220	
221	  for processor specific definitions
222	
223	  - arch/arm/mach-pxa/mfp-pxa3xx.c
224	  - arch/arm/mach-pxa/mfp-pxa2xx.c
225	
226	  for implementation of the pin configuration to take effect for the actual
227	  processor.
228	
229	  Pin Configuration
230	  -----------------
231	
232	  The following comments are copied from mfp.h (see the actual source code
233	  for most updated info)
234	  
235	  /*
236	   * a possible MFP configuration is represented by a 32-bit integer
237	   *
238	   * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
239	   * bit 10..12 - Alternate Function Selection
240	   * bit 13..15 - Drive Strength
241	   * bit 16..18 - Low Power Mode State
242	   * bit 19..20 - Low Power Mode Edge Detection
243	   * bit 21..22 - Run Mode Pull State
244	   *
245	   * to facilitate the definition, the following macros are provided
246	   *
247	   * MFP_CFG_DEFAULT - default MFP configuration value, with
248	   * 		  alternate function = 0,
249	   * 		  drive strength = fast 3mA (MFP_DS03X)
250	   * 		  low power mode = default
251	   * 		  edge detection = none
252	   *
253	   * MFP_CFG	- default MFPR value with alternate function
254	   * MFP_CFG_DRV	- default MFPR value with alternate function and
255	   * 		  pin drive strength
256	   * MFP_CFG_LPM	- default MFPR value with alternate function and
257	   * 		  low power mode
258	   * MFP_CFG_X	- default MFPR value with alternate function,
259	   * 		  pin drive strength and low power mode
260	   */
261	
262	   Examples of pin configurations are:
263	
264	   #define GPIO94_SSP3_RXD		MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
265	
266	   which reads GPIO94 can be configured as SSP3_RXD, with alternate function
267	   selection of 1, driving strength of 0b101, and a float state in low power
268	   modes.
269	
270	   NOTE: this is the default setting of this pin being configured as SSP3_RXD
271	   which can be modified a bit in board code, though it is not recommended to
272	   do so, simply because this default setting is usually carefully encoded,
273	   and is supposed to work in most cases.
274	
275	  Register Settings
276	  -----------------
277	
278	   Register settings on PXA3xx for a pin configuration is actually very
279	   straight-forward, most bits can be converted directly into MFPR value
280	   in a easier way. Two sets of MFPR values are calculated: the run-time
281	   ones and the low power mode ones, to allow different settings.
282	
283	   The conversion from a generic pin configuration to the actual register
284	   settings on PXA2xx is a bit complicated: many registers are involved,
285	   including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see
286	   mfp-pxa2xx.c for how the conversion is made.
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