Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.
1 Altera SoCFPGA ECC Manager 2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. 3 The ECC Manager counts and corrects single bit errors and counts/handles 4 double bit errors which are uncorrectable. 5 6 Cyclone5 and Arria5 ECC Manager 7 Required Properties: 8 - compatible : Should be "altr,socfpga-ecc-manager" 9 - #address-cells: must be 1 10 - #size-cells: must be 1 11 - ranges : standard definition, should translate from local addresses 12 13 Subcomponents: 14 15 L2 Cache ECC 16 Required Properties: 17 - compatible : Should be "altr,socfpga-l2-ecc" 18 - reg : Address and size for ECC error interrupt clear registers. 19 - interrupts : Should be single bit error interrupt, then double bit error 20 interrupt. Note the rising edge type. 21 22 On Chip RAM ECC 23 Required Properties: 24 - compatible : Should be "altr,socfpga-ocram-ecc" 25 - reg : Address and size for ECC error interrupt clear registers. 26 - iram : phandle to On-Chip RAM definition. 27 - interrupts : Should be single bit error interrupt, then double bit error 28 interrupt. Note the rising edge type. 29 30 Example: 31 32 eccmgr: eccmgr@ffd08140 { 33 compatible = "altr,socfpga-ecc-manager"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 ranges; 37 38 l2-ecc@ffd08140 { 39 compatible = "altr,socfpga-l2-ecc"; 40 reg = <0xffd08140 0x4>; 41 interrupts = <0 36 1>, <0 37 1>; 42 }; 43 44 ocram-ecc@ffd08144 { 45 compatible = "altr,socfpga-ocram-ecc"; 46 reg = <0xffd08144 0x4>; 47 iram = <&ocram>; 48 interrupts = <0 178 1>, <0 179 1>; 49 }; 50 }; 51 52 Arria10 SoCFPGA ECC Manager 53 The Arria10 SoC ECC Manager handles the IRQs for each peripheral 54 in a shared register instead of individual IRQs like the Cyclone5 55 and Arria5. Therefore the device tree is different as well. 56 57 Required Properties: 58 - compatible : Should be "altr,socfpga-a10-ecc-manager" 59 - altr,sysgr-syscon : phandle to Arria10 System Manager Block 60 containing the ECC manager registers. 61 - #address-cells: must be 1 62 - #size-cells: must be 1 63 - interrupts : Should be single bit error interrupt, then double bit error 64 interrupt. 65 - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller 66 - #interrupt-cells : must be set to 2. 67 - ranges : standard definition, should translate from local addresses 68 69 Subcomponents: 70 71 L2 Cache ECC 72 Required Properties: 73 - compatible : Should be "altr,socfpga-a10-l2-ecc" 74 - reg : Address and size for ECC error interrupt clear registers. 75 - interrupts : Should be single bit error interrupt, then double bit error 76 interrupt, in this order. 77 78 On-Chip RAM ECC 79 Required Properties: 80 - compatible : Should be "altr,socfpga-a10-ocram-ecc" 81 - reg : Address and size for ECC block registers. 82 - interrupts : Should be single bit error interrupt, then double bit error 83 interrupt, in this order. 84 85 Ethernet FIFO ECC 86 Required Properties: 87 - compatible : Should be "altr,socfpga-eth-mac-ecc" 88 - reg : Address and size for ECC block registers. 89 - altr,ecc-parent : phandle to parent Ethernet node. 90 - interrupts : Should be single bit error interrupt, then double bit error 91 interrupt, in this order. 92 93 NAND FIFO ECC 94 Required Properties: 95 - compatible : Should be "altr,socfpga-nand-ecc" 96 - reg : Address and size for ECC block registers. 97 - altr,ecc-parent : phandle to parent NAND node. 98 - interrupts : Should be single bit error interrupt, then double bit error 99 interrupt, in this order. 100 101 DMA FIFO ECC 102 Required Properties: 103 - compatible : Should be "altr,socfpga-dma-ecc" 104 - reg : Address and size for ECC block registers. 105 - altr,ecc-parent : phandle to parent DMA node. 106 - interrupts : Should be single bit error interrupt, then double bit error 107 interrupt, in this order. 108 109 USB FIFO ECC 110 Required Properties: 111 - compatible : Should be "altr,socfpga-usb-ecc" 112 - reg : Address and size for ECC block registers. 113 - altr,ecc-parent : phandle to parent USB node. 114 - interrupts : Should be single bit error interrupt, then double bit error 115 interrupt, in this order. 116 117 QSPI FIFO ECC 118 Required Properties: 119 - compatible : Should be "altr,socfpga-qspi-ecc" 120 - reg : Address and size for ECC block registers. 121 - altr,ecc-parent : phandle to parent QSPI node. 122 - interrupts : Should be single bit error interrupt, then double bit error 123 interrupt, in this order. 124 125 SDMMC FIFO ECC 126 Required Properties: 127 - compatible : Should be "altr,socfpga-sdmmc-ecc" 128 - reg : Address and size for ECC block registers. 129 - altr,ecc-parent : phandle to parent SD/MMC node. 130 - interrupts : Should be single bit error interrupt, then double bit error 131 interrupt, in this order for port A, and then single bit error interrupt, 132 then double bit error interrupt in this order for port B. 133 134 Example: 135 136 eccmgr: eccmgr@ffd06000 { 137 compatible = "altr,socfpga-a10-ecc-manager"; 138 altr,sysmgr-syscon = <&sysmgr>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, 142 <0 0 IRQ_TYPE_LEVEL_HIGH>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 ranges; 146 147 l2-ecc@ffd06010 { 148 compatible = "altr,socfpga-a10-l2-ecc"; 149 reg = <0xffd06010 0x4>; 150 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, 151 <32 IRQ_TYPE_LEVEL_HIGH>; 152 }; 153 154 ocram-ecc@ff8c3000 { 155 compatible = "altr,socfpga-a10-ocram-ecc"; 156 reg = <0xff8c3000 0x90>; 157 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, 158 <33 IRQ_TYPE_LEVEL_HIGH> ; 159 }; 160 161 emac0-rx-ecc@ff8c0800 { 162 compatible = "altr,socfpga-eth-mac-ecc"; 163 reg = <0xff8c0800 0x400>; 164 altr,ecc-parent = <&gmac0>; 165 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, 166 <36 IRQ_TYPE_LEVEL_HIGH>; 167 }; 168 169 emac0-tx-ecc@ff8c0c00 { 170 compatible = "altr,socfpga-eth-mac-ecc"; 171 reg = <0xff8c0c00 0x400>; 172 altr,ecc-parent = <&gmac0>; 173 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, 174 <37 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 nand-buf-ecc@ff8c2000 { 178 compatible = "altr,socfpga-nand-ecc"; 179 reg = <0xff8c2000 0x400>; 180 altr,ecc-parent = <&nand>; 181 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>, 182 <43 IRQ_TYPE_LEVEL_HIGH>; 183 }; 184 185 nand-rd-ecc@ff8c2400 { 186 compatible = "altr,socfpga-nand-ecc"; 187 reg = <0xff8c2400 0x400>; 188 altr,ecc-parent = <&nand>; 189 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>, 190 <45 IRQ_TYPE_LEVEL_HIGH>; 191 }; 192 193 nand-wr-ecc@ff8c2800 { 194 compatible = "altr,socfpga-nand-ecc"; 195 reg = <0xff8c2800 0x400>; 196 altr,ecc-parent = <&nand>; 197 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 198 <44 IRQ_TYPE_LEVEL_HIGH>; 199 }; 200 201 dma-ecc@ff8c8000 { 202 compatible = "altr,socfpga-dma-ecc"; 203 reg = <0xff8c8000 0x400>; 204 altr,ecc-parent = <&pdma>; 205 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, 206 <42 IRQ_TYPE_LEVEL_HIGH>; 207 208 usb0-ecc@ff8c8800 { 209 compatible = "altr,socfpga-usb-ecc"; 210 reg = <0xff8c8800 0x400>; 211 altr,ecc-parent = <&usb0>; 212 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, 213 <34 IRQ_TYPE_LEVEL_HIGH>; 214 }; 215 216 qspi-ecc@ff8c8400 { 217 compatible = "altr,socfpga-qspi-ecc"; 218 reg = <0xff8c8400 0x400>; 219 altr,ecc-parent = <&qspi>; 220 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 221 <46 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 sdmmc-ecc@ff8c2c00 { 225 compatible = "altr,socfpga-sdmmc-ecc"; 226 reg = <0xff8c2c00 0x400>; 227 altr,ecc-parent = <&mmc>; 228 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, 229 <47 IRQ_TYPE_LEVEL_HIGH>, 230 <16 IRQ_TYPE_LEVEL_HIGH>, 231 <48 IRQ_TYPE_LEVEL_HIGH>; 232 }; 233 };