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Documentation / devicetree / bindings / arm / armada-370-xp-mpic.txt


Based on kernel version 3.15.4. Page generated on 2014-07-07 09:00 EST.

1	Marvell Armada 370, 375, 38x, XP Interrupt Controller
2	-----------------------------------------------------
3	
4	Required properties:
5	- compatible: Should be "marvell,mpic"
6	- interrupt-controller: Identifies the node as an interrupt controller.
7	- msi-controller: Identifies the node as an PCI Message Signaled
8	  Interrupt controller.
9	- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
10	  The cell is the IRQ number
11	
12	- reg: Should contain PMIC registers location and length. First pair
13	  for the main interrupt registers, second pair for the per-CPU
14	  interrupt registers. For this last pair, to be compliant with SMP
15	  support, the "virtual" must be use (For the record, these registers
16	  automatically map to the interrupt controller registers of the
17	  current CPU)
18	
19	Optional properties:
20	
21	- interrupts: If defined, then it indicates that this MPIC is
22	  connected as a slave to another interrupt controller. This is
23	  typically the case on Armada 375 and Armada 38x, where the MPIC is
24	  connected as a slave to the Cortex-A9 GIC. The provided interrupt
25	  indicate to which GIC interrupt the MPIC output is connected.
26	
27	Example:
28	
29	        mpic: interrupt-controller@d0020000 {
30	              compatible = "marvell,mpic";
31	              #interrupt-cells = <1>;
32	              #address-cells = <1>;
33	              #size-cells = <1>;
34	              interrupt-controller;
35	              msi-controller;
36	              reg = <0xd0020a00 0x1d0>,
37	                    <0xd0021070 0x58>;
38	        };
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