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Documentation / devicetree / bindings / bus / ti-gpmc.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:00 EST.

1	Device tree bindings for OMAP general purpose memory controllers (GPMC)
2	
3	The actual devices are instantiated from the child nodes of a GPMC node.
4	
5	Required properties:
6	
7	 - compatible:		Should be set to one of the following:
8	
9				ti,omap2420-gpmc (omap2420)
10				ti,omap2430-gpmc (omap2430)
11				ti,omap3430-gpmc (omap3430 & omap3630)
12				ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13				ti,am3352-gpmc   (am335x devices)
14	
15	 - reg:			A resource specifier for the register space
16				(see the example below)
17	 - ti,hwmods:		Should be set to "ti,gpmc" until the DT transition is
18				completed.
19	 - #address-cells:	Must be set to 2 to allow memory address translation
20	 - #size-cells:		Must be set to 1 to allow CS address passing
21	 - gpmc,num-cs:		The maximum number of chip-select lines that controller
22				can support.
23	 - gpmc,num-waitpins:	The maximum number of wait pins that controller can
24				support.
25	 - ranges:		Must be set up to reflect the memory layout with four
26				integer values for each chip-select line in use:
27	
28				   <cs-number> 0 <physical address of mapping> <size>
29	
30				Currently, calculated values derived from the contents
31				of the per-CS register GPMC_CONFIG7 (as set up by the
32				bootloader) are used for the physical address decoding.
33				As this will change in the future, filling correct
34				values here is a requirement.
35	
36	Timing properties for child nodes. All are optional and default to 0.
37	
38	 - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds
39	
40	 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
41	 - gpmc,cs-on-ns:	Assertion time
42	 - gpmc,cs-rd-off-ns:	Read deassertion time
43	 - gpmc,cs-wr-off-ns:	Write deassertion time
44	
45	 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
46	 - gpmc,adv-on-ns:	Assertion time
47	 - gpmc,adv-rd-off-ns:	Read deassertion time
48	 - gpmc,adv-wr-off-ns:	Write deassertion time
49	
50	 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
51	 - gpmc,we-on-ns	Assertion time
52	 - gpmc,we-off-ns:	Deassertion time
53	
54	 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
55	 - gpmc,oe-on-ns:	Assertion time
56	 - gpmc,oe-off-ns:	Deassertion time
57	
58	 Access time and cycle time timings (in nanoseconds) corresponding to
59	 GPMC_CONFIG5:
60	 - gpmc,page-burst-access-ns: 	Multiple access word delay
61	 - gpmc,access-ns:		Start-cycle to first data valid delay
62	 - gpmc,rd-cycle-ns:		Total read cycle time
63	 - gpmc,wr-cycle-ns:		Total write cycle time
64	 - gpmc,bus-turnaround-ns:	Turn-around time between successive accesses
65	 - gpmc,cycle2cycle-delay-ns:	Delay between chip-select pulses
66	 - gpmc,clk-activation-ns: 	GPMC clock activation time
67	 - gpmc,wait-monitoring-ns:	Start of wait monitoring with regard to valid
68					data
69	
70	Boolean timing parameters. If property is present parameter enabled and
71	disabled if omitted:
72	 - gpmc,adv-extra-delay:	ADV signal is delayed by half GPMC clock
73	 - gpmc,cs-extra-delay:		CS signal is delayed by half GPMC clock
74	 - gpmc,cycle2cycle-diffcsen:	Add "cycle2cycle-delay" between successive
75					accesses to a different CS
76	 - gpmc,cycle2cycle-samecsen:	Add "cycle2cycle-delay" between successive
77					accesses to the same CS
78	 - gpmc,oe-extra-delay:		OE signal is delayed by half GPMC clock
79	 - gpmc,we-extra-delay:		WE signal is delayed by half GPMC clock
80	 - gpmc,time-para-granularity:	Multiply all access times by 2
81	
82	The following are only applicable to OMAP3+ and AM335x:
83	 - gpmc,wr-access-ns:		In synchronous write mode, for single or
84					burst accesses, defines the number of
85					GPMC_FCLK cycles from start access time
86					to the GPMC_CLK rising edge used by the
87					memory device for the first data capture.
88	 - gpmc,wr-data-mux-bus-ns:	In address-data multiplex mode, specifies
89					the time when the first data is driven on
90					the address-data bus.
91	
92	GPMC chip-select settings properties for child nodes. All are optional.
93	
94	- gpmc,burst-length	Page/burst length. Must be 4, 8 or 16.
95	- gpmc,burst-wrap	Enables wrap bursting
96	- gpmc,burst-read	Enables read page/burst mode
97	- gpmc,burst-write	Enables write page/burst mode
98	- gpmc,device-width	Total width of device(s) connected to a GPMC
99				chip-select in bytes. The GPMC supports 8-bit
100				and 16-bit devices and so this property must be
101				1 or 2.
102	- gpmc,mux-add-data	Address and data multiplexing configuration.
103				Valid values are 1 for address-address-data
104				multiplexing mode and 2 for address-data
105				multiplexing mode.
106	- gpmc,sync-read	Enables synchronous read. Defaults to asynchronous
107				is this is not set.
108	- gpmc,sync-write	Enables synchronous writes. Defaults to asynchronous
109				is this is not set.
110	- gpmc,wait-pin		Wait-pin used by client. Must be less than
111				"gpmc,num-waitpins".
112	- gpmc,wait-on-read	Enables wait monitoring on reads.
113	- gpmc,wait-on-write	Enables wait monitoring on writes.
114	
115	Example for an AM33xx board:
116	
117		gpmc: gpmc@50000000 {
118			compatible = "ti,am3352-gpmc";
119			ti,hwmods = "gpmc";
120			reg = <0x50000000 0x2000>;
121			interrupts = <100>;
122	
123			gpmc,num-cs = <8>;
124			gpmc,num-waitpins = <2>;
125			#address-cells = <2>;
126			#size-cells = <1>;
127			ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
128	
129			/* child nodes go here */
130		};
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