Based on kernel version 4.6.2. Page generated on 2016-06-08 13:02 EST.
1 Device tree bindings for OMAP general purpose memory controllers (GPMC) 2 3 The actual devices are instantiated from the child nodes of a GPMC node. 4 5 Required properties: 6 7 - compatible: Should be set to one of the following: 8 9 ti,omap2420-gpmc (omap2420) 10 ti,omap2430-gpmc (omap2430) 11 ti,omap3430-gpmc (omap3430 & omap3630) 12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) 13 ti,am3352-gpmc (am335x devices) 14 15 - reg: A resource specifier for the register space 16 (see the example below) 17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is 18 completed. 19 - #address-cells: Must be set to 2 to allow memory address translation 20 - #size-cells: Must be set to 1 to allow CS address passing 21 - gpmc,num-cs: The maximum number of chip-select lines that controller 22 can support. 23 - gpmc,num-waitpins: The maximum number of wait pins that controller can 24 support. 25 - ranges: Must be set up to reflect the memory layout with four 26 integer values for each chip-select line in use: 27 28 <cs-number> 0 <physical address of mapping> <size> 29 30 Currently, calculated values derived from the contents 31 of the per-CS register GPMC_CONFIG7 (as set up by the 32 bootloader) are used for the physical address decoding. 33 As this will change in the future, filling correct 34 values here is a requirement. 35 36 Timing properties for child nodes. All are optional and default to 0. 37 38 - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds 39 40 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: 41 - gpmc,cs-on-ns: Assertion time 42 - gpmc,cs-rd-off-ns: Read deassertion time 43 - gpmc,cs-wr-off-ns: Write deassertion time 44 45 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: 46 - gpmc,adv-on-ns: Assertion time 47 - gpmc,adv-rd-off-ns: Read deassertion time 48 - gpmc,adv-wr-off-ns: Write deassertion time 49 - gpmc,adv-aad-mux-on-ns: Assertion time for AAD 50 - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD 51 - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD 52 53 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: 54 - gpmc,we-on-ns Assertion time 55 - gpmc,we-off-ns: Deassertion time 56 57 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: 58 - gpmc,oe-on-ns: Assertion time 59 - gpmc,oe-off-ns: Deassertion time 60 - gpmc,oe-aad-mux-on-ns: Assertion time for AAD 61 - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD 62 63 Access time and cycle time timings (in nanoseconds) corresponding to 64 GPMC_CONFIG5: 65 - gpmc,page-burst-access-ns: Multiple access word delay 66 - gpmc,access-ns: Start-cycle to first data valid delay 67 - gpmc,rd-cycle-ns: Total read cycle time 68 - gpmc,wr-cycle-ns: Total write cycle time 69 - gpmc,bus-turnaround-ns: Turn-around time between successive accesses 70 - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses 71 - gpmc,clk-activation-ns: GPMC clock activation time 72 - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid 73 data 74 75 Boolean timing parameters. If property is present parameter enabled and 76 disabled if omitted: 77 - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock 78 - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock 79 - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive 80 accesses to a different CS 81 - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive 82 accesses to the same CS 83 - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock 84 - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock 85 - gpmc,time-para-granularity: Multiply all access times by 2 86 87 The following are only applicable to OMAP3+ and AM335x: 88 - gpmc,wr-access-ns: In synchronous write mode, for single or 89 burst accesses, defines the number of 90 GPMC_FCLK cycles from start access time 91 to the GPMC_CLK rising edge used by the 92 memory device for the first data capture. 93 - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies 94 the time when the first data is driven on 95 the address-data bus. 96 97 GPMC chip-select settings properties for child nodes. All are optional. 98 99 - gpmc,burst-length Page/burst length. Must be 4, 8 or 16. 100 - gpmc,burst-wrap Enables wrap bursting 101 - gpmc,burst-read Enables read page/burst mode 102 - gpmc,burst-write Enables write page/burst mode 103 - gpmc,device-width Total width of device(s) connected to a GPMC 104 chip-select in bytes. The GPMC supports 8-bit 105 and 16-bit devices and so this property must be 106 1 or 2. 107 - gpmc,mux-add-data Address and data multiplexing configuration. 108 Valid values are 1 for address-address-data 109 multiplexing mode and 2 for address-data 110 multiplexing mode. 111 - gpmc,sync-read Enables synchronous read. Defaults to asynchronous 112 is this is not set. 113 - gpmc,sync-write Enables synchronous writes. Defaults to asynchronous 114 is this is not set. 115 - gpmc,wait-pin Wait-pin used by client. Must be less than 116 "gpmc,num-waitpins". 117 - gpmc,wait-on-read Enables wait monitoring on reads. 118 - gpmc,wait-on-write Enables wait monitoring on writes. 119 120 Example for an AM33xx board: 121 122 gpmc: gpmc@50000000 { 123 compatible = "ti,am3352-gpmc"; 124 ti,hwmods = "gpmc"; 125 reg = <0x50000000 0x2000>; 126 interrupts = <100>; 127 128 gpmc,num-cs = <8>; 129 gpmc,num-waitpins = <2>; 130 #address-cells = <2>; 131 #size-cells = <1>; 132 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ 133 134 /* child nodes go here */ 135 };