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Documentation / devicetree / bindings / clock / at91-clock.txt




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Based on kernel version 3.19. Page generated on 2015-02-13 21:17 EST.

1	Device Tree Clock bindings for arch-at91
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"atmel,at91sam9x5-sckc":
10			at91 SCKC (Slow Clock Controller)
11			This node contains the slow clock definitions.
12	
13		"atmel,at91sam9x5-clk-slow-osc":
14			at91 slow oscillator
15	
16		"atmel,at91sam9x5-clk-slow-rc-osc":
17			at91 internal slow RC oscillator
18	
19		"atmel,at91rm9200-pmc" or
20		"atmel,at91sam9g45-pmc" or
21		"atmel,at91sam9n12-pmc" or
22		"atmel,at91sam9x5-pmc" or
23		"atmel,sama5d3-pmc":
24			at91 PMC (Power Management Controller)
25			All at91 specific clocks (clocks defined below) must be child
26			node of the PMC node.
27	
28		"atmel,at91sam9x5-clk-slow" (under sckc node)
29		or
30		"atmel,at91sam9260-clk-slow" (under pmc node):
31			at91 slow clk
32	
33		"atmel,at91rm9200-clk-main-osc"
34		"atmel,at91sam9x5-clk-main-rc-osc"
35			at91 main clk sources
36	
37		"atmel,at91sam9x5-clk-main"
38		"atmel,at91rm9200-clk-main":
39			at91 main clock
40	
41		"atmel,at91rm9200-clk-master" or
42		"atmel,at91sam9x5-clk-master":
43			at91 master clock
44	
45		"atmel,at91sam9x5-clk-peripheral" or
46		"atmel,at91rm9200-clk-peripheral":
47			at91 peripheral clocks
48	
49		"atmel,at91rm9200-clk-pll" or
50		"atmel,at91sam9g45-clk-pll" or
51		"atmel,at91sam9g20-clk-pllb" or
52		"atmel,sama5d3-clk-pll":
53			at91 pll clocks
54	
55		"atmel,at91sam9x5-clk-plldiv":
56			at91 plla divisor
57	
58		"atmel,at91rm9200-clk-programmable" or
59		"atmel,at91sam9g45-clk-programmable" or
60		"atmel,at91sam9x5-clk-programmable":
61			at91 programmable clocks
62	
63		"atmel,at91sam9x5-clk-smd":
64			at91 SMD (Soft Modem) clock
65	
66		"atmel,at91rm9200-clk-system":
67			at91 system clocks
68	
69		"atmel,at91rm9200-clk-usb" or
70		"atmel,at91sam9x5-clk-usb" or
71		"atmel,at91sam9n12-clk-usb":
72			at91 usb clock
73	
74		"atmel,at91sam9x5-clk-utmi":
75			at91 utmi clock
76	
77		"atmel,sama5d4-clk-h32mx":
78			at91 h32mx clock
79	
80	Required properties for SCKC node:
81	- reg : defines the IO memory reserved for the SCKC.
82	- #size-cells : shall be 0 (reg is used to encode clk id).
83	- #address-cells : shall be 1 (reg is used to encode clk id).
84	
85	
86	For example:
87		sckc: sckc@fffffe50 {
88			compatible = "atmel,sama5d3-pmc";
89			reg = <0xfffffe50 0x4>
90			#size-cells = <0>;
91			#address-cells = <1>;
92	
93			/* put at91 slow clocks here */
94		};
95	
96	
97	Required properties for internal slow RC oscillator:
98	- #clock-cells : from common clock binding; shall be set to 0.
99	- clock-frequency : define the internal RC oscillator frequency.
100	
101	Optional properties:
102	- clock-accuracy : define the internal RC oscillator accuracy.
103	
104	For example:
105		slow_rc_osc: slow_rc_osc {
106			compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
107			clock-frequency = <32768>;
108			clock-accuracy = <50000000>;
109		};
110	
111	Required properties for slow oscillator:
112	- #clock-cells : from common clock binding; shall be set to 0.
113	- clocks : shall encode the main osc source clk sources (see atmel datasheet).
114	
115	Optional properties:
116	- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
117	  provided on XIN.
118	
119	For example:
120		slow_osc: slow_osc {
121			compatible = "atmel,at91rm9200-clk-slow-osc";
122			#clock-cells = <0>;
123			clocks = <&slow_xtal>;
124		};
125	
126	Required properties for slow clock:
127	- #clock-cells : from common clock binding; shall be set to 0.
128	- clocks : shall encode the slow clk sources (see atmel datasheet).
129	
130	For example:
131		clk32k: slck {
132			compatible = "atmel,at91sam9x5-clk-slow";
133			#clock-cells = <0>;
134			clocks = <&slow_rc_osc &slow_osc>;
135		};
136	
137	Required properties for PMC node:
138	- reg : defines the IO memory reserved for the PMC.
139	- #size-cells : shall be 0 (reg is used to encode clk id).
140	- #address-cells : shall be 1 (reg is used to encode clk id).
141	- interrupts : shall be set to PMC interrupt line.
142	- interrupt-controller : tell that the PMC is an interrupt controller.
143	- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
144		and reflect the bit position in the PMC_ER/DR/SR registers.
145		You can use the dt macros defined in dt-bindings/clock/at91.h.
146		0 (AT91_PMC_MOSCS) -> main oscillator ready
147		1 (AT91_PMC_LOCKA) -> PLL A ready
148		2 (AT91_PMC_LOCKB) -> PLL B ready
149		3 (AT91_PMC_MCKRDY) -> master clock ready
150		6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
151		8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
152		16 (AT91_PMC_MOSCSELS) -> main oscillator selected
153		17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
154		18 (AT91_PMC_CFDEV) -> clock failure detected
155	
156	For example:
157		pmc: pmc@fffffc00 {
158			compatible = "atmel,sama5d3-pmc";
159			interrupts = <1 4 7>;
160			interrupt-controller;
161			#interrupt-cells = <2>;
162			#size-cells = <0>;
163			#address-cells = <1>;
164	
165			/* put at91 clocks here */
166		};
167	
168	Required properties for main clock internal RC oscillator:
169	- interrupt-parent : must reference the PMC node.
170	- interrupts : shall be set to "<0>".
171	- clock-frequency : define the internal RC oscillator frequency.
172	
173	Optional properties:
174	- clock-accuracy : define the internal RC oscillator accuracy.
175	
176	For example:
177		main_rc_osc: main_rc_osc {
178			compatible = "atmel,at91sam9x5-clk-main-rc-osc";
179			interrupt-parent = <&pmc>;
180			interrupts = <0>;
181			clock-frequency = <12000000>;
182			clock-accuracy = <50000000>;
183		};
184	
185	Required properties for main clock oscillator:
186	- interrupt-parent : must reference the PMC node.
187	- interrupts : shall be set to "<0>".
188	- #clock-cells : from common clock binding; shall be set to 0.
189	- clocks : shall encode the main osc source clk sources (see atmel datasheet).
190	
191	Optional properties:
192	- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
193	  on XIN.
194	
195	  clock signal is directly provided on XIN pin.
196	
197	For example:
198		main_osc: main_osc {
199			compatible = "atmel,at91rm9200-clk-main-osc";
200			interrupt-parent = <&pmc>;
201			interrupts = <0>;
202			#clock-cells = <0>;
203			clocks = <&main_xtal>;
204		};
205	
206	Required properties for main clock:
207	- interrupt-parent : must reference the PMC node.
208	- interrupts : shall be set to "<0>".
209	- #clock-cells : from common clock binding; shall be set to 0.
210	- clocks : shall encode the main clk sources (see atmel datasheet).
211	
212	For example:
213		main: mainck {
214			compatible = "atmel,at91sam9x5-clk-main";
215			interrupt-parent = <&pmc>;
216			interrupts = <0>;
217			#clock-cells = <0>;
218			clocks = <&main_rc_osc &main_osc>;
219		};
220	
221	Required properties for master clock:
222	- interrupt-parent : must reference the PMC node.
223	- interrupts : shall be set to "<3>".
224	- #clock-cells : from common clock binding; shall be set to 0.
225	- clocks : shall be the master clock sources (see atmel datasheet) phandles.
226		e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
227	- atmel,clk-output-range : minimum and maximum clock frequency (two u32
228				   fields).
229		   e.g. output = <0 133000000>; <=> 0 to 133MHz.
230	- atmel,clk-divisors : master clock divisors table (four u32 fields).
231			0 <=> reserved value.
232			e.g. divisors = <1 2 4 6>;
233	- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
234					    PRES field as CLOCK_DIV3 (e.g sam9x5).
235	
236	For example:
237		mck: mck {
238			compatible = "atmel,at91rm9200-clk-master";
239			interrupt-parent = <&pmc>;
240			interrupts = <3>;
241			#clock-cells = <0>;
242			atmel,clk-output-range = <0 133000000>;
243			atmel,clk-divisors = <1 2 4 0>;
244		};
245	
246	Required properties for peripheral clocks:
247	- #size-cells : shall be 0 (reg is used to encode clk id).
248	- #address-cells : shall be 1 (reg is used to encode clk id).
249	- clocks : shall be the master clock phandle.
250		e.g. clocks = <&mck>;
251	- name: device tree node describing a specific system clock.
252		* #clock-cells : from common clock binding; shall be set to 0.
253		* reg: peripheral id. See Atmel's datasheets to get a full
254		  list of peripheral ids.
255		* atmel,clk-output-range : minimum and maximum clock frequency
256		  (two u32 fields). Only valid on at91sam9x5-clk-peripheral
257		  compatible IPs.
258	
259	For example:
260		periph: periphck {
261			compatible = "atmel,at91sam9x5-clk-peripheral";
262			#size-cells = <0>;
263			#address-cells = <1>;
264			clocks = <&mck>;
265	
266			ssc0_clk {
267				#clock-cells = <0>;
268				reg = <2>;
269				atmel,clk-output-range = <0 133000000>;
270			};
271	
272			usart0_clk {
273				#clock-cells = <0>;
274				reg = <3>;
275				atmel,clk-output-range = <0 66000000>;
276			};
277		};
278	
279	
280	Required properties for pll clocks:
281	- interrupt-parent : must reference the PMC node.
282	- interrupts : shall be set to "<1>".
283	- #clock-cells : from common clock binding; shall be set to 0.
284	- clocks : shall be the main clock phandle.
285	- reg : pll id.
286		0 -> PLL A
287		1 -> PLL B
288	- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
289				  fields).
290		  e.g. input = <1 32000000>; <=> 1 to 32MHz.
291	- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
292					      range description. Sould be set to 2, 3
293					      or 4.
294		* 1st and 2nd cells represent the frequency range (min-max).
295		* 3rd cell is optional and represents the OUT field value for the given
296		  range.
297		* 4th cell is optional and represents the ICPLL field (PLLICPR
298		  register)
299	- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
300					depending on #atmel,pll-output-range-cells
301					property value.
302	
303	For example:
304		plla: pllack {
305			compatible = "atmel,at91sam9g45-clk-pll";
306			interrupt-parent = <&pmc>;
307			interrupts = <1>;
308			#clock-cells = <0>;
309			clocks = <&main>;
310			reg = <0>;
311			atmel,clk-input-range = <2000000 32000000>;
312			#atmel,pll-clk-output-range-cells = <4>;
313			atmel,pll-clk-output-ranges = <74500000 800000000 0 0
314						       69500000 750000000 1 0
315						       64500000 700000000 2 0
316						       59500000 650000000 3 0
317						       54500000 600000000 0 1
318						       49500000 550000000 1 1
319						       44500000 500000000 2 1
320						       40000000 450000000 3 1>;
321		};
322	
323	Required properties for plldiv clocks (plldiv = pll / 2):
324	- #clock-cells : from common clock binding; shall be set to 0.
325	- clocks : shall be the plla clock phandle.
326	
327	The pll divisor is equal to 2 and cannot be changed.
328	
329	For example:
330		plladiv: plladivck {
331			compatible = "atmel,at91sam9x5-clk-plldiv";
332			#clock-cells = <0>;
333			clocks = <&plla>;
334		};
335	
336	Required properties for programmable clocks:
337	- interrupt-parent : must reference the PMC node.
338	- #size-cells : shall be 0 (reg is used to encode clk id).
339	- #address-cells : shall be 1 (reg is used to encode clk id).
340	- clocks : shall be the programmable clock source phandles.
341		e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
342	- name: device tree node describing a specific prog clock.
343		* #clock-cells : from common clock binding; shall be set to 0.
344		* reg : programmable clock id (register offset from  PCKx
345				 register).
346		* interrupts : shall be set to "<(8 + id)>".
347	
348	For example:
349		prog: progck {
350			compatible = "atmel,at91sam9g45-clk-programmable";
351			#size-cells = <0>;
352			#address-cells = <1>;
353			interrupt-parent = <&pmc>;
354			clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
355	
356			prog0 {
357				#clock-cells = <0>;
358				reg = <0>;
359				interrupts = <8>;
360			};
361	
362			prog1 {
363				#clock-cells = <0>;
364				reg = <1>;
365				interrupts = <9>;
366			};
367		};
368	
369	
370	Required properties for smd clock:
371	- #clock-cells : from common clock binding; shall be set to 0.
372	- clocks : shall be the smd clock source phandles.
373		e.g. clocks = <&plladiv>, <&utmi>;
374	
375	For example:
376		smd: smdck {
377			compatible = "atmel,at91sam9x5-clk-smd";
378			#clock-cells = <0>;
379			clocks = <&plladiv>, <&utmi>;
380		};
381	
382	Required properties for system clocks:
383	- #size-cells : shall be 0 (reg is used to encode clk id).
384	- #address-cells : shall be 1 (reg is used to encode clk id).
385	- name: device tree node describing a specific system clock.
386		* #clock-cells : from common clock binding; shall be set to 0.
387		* reg: system clock id (bit position in SCER/SCDR/SCSR registers).
388		      See Atmel's datasheet to get a full list of system clock ids.
389	
390	For example:
391		system: systemck {
392			compatible = "atmel,at91rm9200-clk-system";
393			#address-cells = <1>;
394			#size-cells = <0>;
395	
396			ddrck {
397				#clock-cells = <0>;
398				reg = <2>;
399				clocks = <&mck>;
400			};
401	
402			uhpck {
403				#clock-cells = <0>;
404				reg = <6>;
405				clocks = <&usb>;
406			};
407	
408			udpck {
409				#clock-cells = <0>;
410				reg = <7>;
411				clocks = <&usb>;
412			};
413		};
414	
415	
416	Required properties for usb clock:
417	- #clock-cells : from common clock binding; shall be set to 0.
418	- clocks : shall be the smd clock source phandles.
419		e.g. clocks = <&pllb>;
420	- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
421		usb clock divisor table.
422		e.g. divisors = <1 2 4 0>;
423	
424	For example:
425		usb: usbck {
426			compatible = "atmel,at91sam9x5-clk-usb";
427			#clock-cells = <0>;
428			clocks = <&plladiv>, <&utmi>;
429		};
430	
431		usb: usbck {
432			compatible = "atmel,at91rm9200-clk-usb";
433			#clock-cells = <0>;
434			clocks = <&pllb>;
435			atmel,clk-divisors = <1 2 4 0>;
436		};
437	
438	
439	Required properties for utmi clock:
440	- interrupt-parent : must reference the PMC node.
441	- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
442	- #clock-cells : from common clock binding; shall be set to 0.
443	- clocks : shall be the main clock source phandle.
444	
445	For example:
446		utmi: utmick {
447			compatible = "atmel,at91sam9x5-clk-utmi";
448			interrupt-parent = <&pmc>;
449			interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
450			#clock-cells = <0>;
451			clocks = <&main>;
452		};
453	
454	Required properties for 32 bits bus Matrix clock (h32mx clock):
455	- #clock-cells : from common clock binding; shall be set to 0.
456	- clocks : shall be the master clock source phandle.
457	
458	For example:
459		h32ck: h32mxck {
460			#clock-cells = <0>;
461			compatible = "atmel,sama5d4-clk-h32mx";
462			clocks = <&mck>;
463		};
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