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Documentation / devicetree / bindings / clock / at91-clock.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	Device Tree Clock bindings for arch-at91
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"atmel,at91sam9x5-sckc":
10			at91 SCKC (Slow Clock Controller)
11			This node contains the slow clock definitions.
12	
13		"atmel,at91sam9x5-clk-slow-osc":
14			at91 slow oscillator
15	
16		"atmel,at91sam9x5-clk-slow-rc-osc":
17			at91 internal slow RC oscillator
18	
19		"atmel,at91rm9200-pmc" or
20		"atmel,at91sam9g45-pmc" or
21		"atmel,at91sam9n12-pmc" or
22		"atmel,at91sam9x5-pmc" or
23		"atmel,sama5d3-pmc":
24			at91 PMC (Power Management Controller)
25			All at91 specific clocks (clocks defined below) must be child
26			node of the PMC node.
27	
28		"atmel,at91sam9x5-clk-slow" (under sckc node)
29		or
30		"atmel,at91sam9260-clk-slow" (under pmc node):
31			at91 slow clk
32	
33		"atmel,at91rm9200-clk-main-osc"
34		"atmel,at91sam9x5-clk-main-rc-osc"
35			at91 main clk sources
36	
37		"atmel,at91sam9x5-clk-main"
38		"atmel,at91rm9200-clk-main":
39			at91 main clock
40	
41		"atmel,at91rm9200-clk-master" or
42		"atmel,at91sam9x5-clk-master":
43			at91 master clock
44	
45		"atmel,at91sam9x5-clk-peripheral" or
46		"atmel,at91rm9200-clk-peripheral":
47			at91 peripheral clocks
48	
49		"atmel,at91rm9200-clk-pll" or
50		"atmel,at91sam9g45-clk-pll" or
51		"atmel,at91sam9g20-clk-pllb" or
52		"atmel,sama5d3-clk-pll":
53			at91 pll clocks
54	
55		"atmel,at91sam9x5-clk-plldiv":
56			at91 plla divisor
57	
58		"atmel,at91rm9200-clk-programmable" or
59		"atmel,at91sam9g45-clk-programmable" or
60		"atmel,at91sam9x5-clk-programmable":
61			at91 programmable clocks
62	
63		"atmel,at91sam9x5-clk-smd":
64			at91 SMD (Soft Modem) clock
65	
66		"atmel,at91rm9200-clk-system":
67			at91 system clocks
68	
69		"atmel,at91rm9200-clk-usb" or
70		"atmel,at91sam9x5-clk-usb" or
71		"atmel,at91sam9n12-clk-usb":
72			at91 usb clock
73	
74		"atmel,at91sam9x5-clk-utmi":
75			at91 utmi clock
76	
77	Required properties for SCKC node:
78	- reg : defines the IO memory reserved for the SCKC.
79	- #size-cells : shall be 0 (reg is used to encode clk id).
80	- #address-cells : shall be 1 (reg is used to encode clk id).
81	
82	
83	For example:
84		sckc: sckc@fffffe50 {
85			compatible = "atmel,sama5d3-pmc";
86			reg = <0xfffffe50 0x4>
87			#size-cells = <0>;
88			#address-cells = <1>;
89	
90			/* put at91 slow clocks here */
91		};
92	
93	
94	Required properties for internal slow RC oscillator:
95	- #clock-cells : from common clock binding; shall be set to 0.
96	- clock-frequency : define the internal RC oscillator frequency.
97	
98	Optional properties:
99	- clock-accuracy : define the internal RC oscillator accuracy.
100	
101	For example:
102		slow_rc_osc: slow_rc_osc {
103			compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
104			clock-frequency = <32768>;
105			clock-accuracy = <50000000>;
106		};
107	
108	Required properties for slow oscillator:
109	- #clock-cells : from common clock binding; shall be set to 0.
110	- clocks : shall encode the main osc source clk sources (see atmel datasheet).
111	
112	Optional properties:
113	- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
114	  provided on XIN.
115	
116	For example:
117		slow_osc: slow_osc {
118			compatible = "atmel,at91rm9200-clk-slow-osc";
119			#clock-cells = <0>;
120			clocks = <&slow_xtal>;
121		};
122	
123	Required properties for slow clock:
124	- #clock-cells : from common clock binding; shall be set to 0.
125	- clocks : shall encode the slow clk sources (see atmel datasheet).
126	
127	For example:
128		clk32k: slck {
129			compatible = "atmel,at91sam9x5-clk-slow";
130			#clock-cells = <0>;
131			clocks = <&slow_rc_osc &slow_osc>;
132		};
133	
134	Required properties for PMC node:
135	- reg : defines the IO memory reserved for the PMC.
136	- #size-cells : shall be 0 (reg is used to encode clk id).
137	- #address-cells : shall be 1 (reg is used to encode clk id).
138	- interrupts : shall be set to PMC interrupt line.
139	- interrupt-controller : tell that the PMC is an interrupt controller.
140	- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
141		and reflect the bit position in the PMC_ER/DR/SR registers.
142		You can use the dt macros defined in dt-bindings/clock/at91.h.
143		0 (AT91_PMC_MOSCS) -> main oscillator ready
144		1 (AT91_PMC_LOCKA) -> PLL A ready
145		2 (AT91_PMC_LOCKB) -> PLL B ready
146		3 (AT91_PMC_MCKRDY) -> master clock ready
147		6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
148		8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
149		16 (AT91_PMC_MOSCSELS) -> main oscillator selected
150		17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
151		18 (AT91_PMC_CFDEV) -> clock failure detected
152	
153	For example:
154		pmc: pmc@fffffc00 {
155			compatible = "atmel,sama5d3-pmc";
156			interrupts = <1 4 7>;
157			interrupt-controller;
158			#interrupt-cells = <2>;
159			#size-cells = <0>;
160			#address-cells = <1>;
161	
162			/* put at91 clocks here */
163		};
164	
165	Required properties for main clock internal RC oscillator:
166	- interrupt-parent : must reference the PMC node.
167	- interrupts : shall be set to "<0>".
168	- clock-frequency : define the internal RC oscillator frequency.
169	
170	Optional properties:
171	- clock-accuracy : define the internal RC oscillator accuracy.
172	
173	For example:
174		main_rc_osc: main_rc_osc {
175			compatible = "atmel,at91sam9x5-clk-main-rc-osc";
176			interrupt-parent = <&pmc>;
177			interrupts = <0>;
178			clock-frequency = <12000000>;
179			clock-accuracy = <50000000>;
180		};
181	
182	Required properties for main clock oscillator:
183	- interrupt-parent : must reference the PMC node.
184	- interrupts : shall be set to "<0>".
185	- #clock-cells : from common clock binding; shall be set to 0.
186	- clocks : shall encode the main osc source clk sources (see atmel datasheet).
187	
188	Optional properties:
189	- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
190	  on XIN.
191	
192	  clock signal is directly provided on XIN pin.
193	
194	For example:
195		main_osc: main_osc {
196			compatible = "atmel,at91rm9200-clk-main-osc";
197			interrupt-parent = <&pmc>;
198			interrupts = <0>;
199			#clock-cells = <0>;
200			clocks = <&main_xtal>;
201		};
202	
203	Required properties for main clock:
204	- interrupt-parent : must reference the PMC node.
205	- interrupts : shall be set to "<0>".
206	- #clock-cells : from common clock binding; shall be set to 0.
207	- clocks : shall encode the main clk sources (see atmel datasheet).
208	
209	For example:
210		main: mainck {
211			compatible = "atmel,at91sam9x5-clk-main";
212			interrupt-parent = <&pmc>;
213			interrupts = <0>;
214			#clock-cells = <0>;
215			clocks = <&main_rc_osc &main_osc>;
216		};
217	
218	Required properties for master clock:
219	- interrupt-parent : must reference the PMC node.
220	- interrupts : shall be set to "<3>".
221	- #clock-cells : from common clock binding; shall be set to 0.
222	- clocks : shall be the master clock sources (see atmel datasheet) phandles.
223		e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
224	- atmel,clk-output-range : minimum and maximum clock frequency (two u32
225				   fields).
226		   e.g. output = <0 133000000>; <=> 0 to 133MHz.
227	- atmel,clk-divisors : master clock divisors table (four u32 fields).
228			0 <=> reserved value.
229			e.g. divisors = <1 2 4 6>;
230	- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
231					    PRES field as CLOCK_DIV3 (e.g sam9x5).
232	
233	For example:
234		mck: mck {
235			compatible = "atmel,at91rm9200-clk-master";
236			interrupt-parent = <&pmc>;
237			interrupts = <3>;
238			#clock-cells = <0>;
239			atmel,clk-output-range = <0 133000000>;
240			atmel,clk-divisors = <1 2 4 0>;
241		};
242	
243	Required properties for peripheral clocks:
244	- #size-cells : shall be 0 (reg is used to encode clk id).
245	- #address-cells : shall be 1 (reg is used to encode clk id).
246	- clocks : shall be the master clock phandle.
247		e.g. clocks = <&mck>;
248	- name: device tree node describing a specific system clock.
249		* #clock-cells : from common clock binding; shall be set to 0.
250		* reg: peripheral id. See Atmel's datasheets to get a full
251		  list of peripheral ids.
252		* atmel,clk-output-range : minimum and maximum clock frequency
253		  (two u32 fields). Only valid on at91sam9x5-clk-peripheral
254		  compatible IPs.
255	
256	For example:
257		periph: periphck {
258			compatible = "atmel,at91sam9x5-clk-peripheral";
259			#size-cells = <0>;
260			#address-cells = <1>;
261			clocks = <&mck>;
262	
263			ssc0_clk {
264				#clock-cells = <0>;
265				reg = <2>;
266				atmel,clk-output-range = <0 133000000>;
267			};
268	
269			usart0_clk {
270				#clock-cells = <0>;
271				reg = <3>;
272				atmel,clk-output-range = <0 66000000>;
273			};
274		};
275	
276	
277	Required properties for pll clocks:
278	- interrupt-parent : must reference the PMC node.
279	- interrupts : shall be set to "<1>".
280	- #clock-cells : from common clock binding; shall be set to 0.
281	- clocks : shall be the main clock phandle.
282	- reg : pll id.
283		0 -> PLL A
284		1 -> PLL B
285	- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
286				  fields).
287		  e.g. input = <1 32000000>; <=> 1 to 32MHz.
288	- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
289					      range description. Sould be set to 2, 3
290					      or 4.
291		* 1st and 2nd cells represent the frequency range (min-max).
292		* 3rd cell is optional and represents the OUT field value for the given
293		  range.
294		* 4th cell is optional and represents the ICPLL field (PLLICPR
295		  register)
296	- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
297					depending on #atmel,pll-output-range-cells
298					property value.
299	
300	For example:
301		plla: pllack {
302			compatible = "atmel,at91sam9g45-clk-pll";
303			interrupt-parent = <&pmc>;
304			interrupts = <1>;
305			#clock-cells = <0>;
306			clocks = <&main>;
307			reg = <0>;
308			atmel,clk-input-range = <2000000 32000000>;
309			#atmel,pll-clk-output-range-cells = <4>;
310			atmel,pll-clk-output-ranges = <74500000 800000000 0 0
311						       69500000 750000000 1 0
312						       64500000 700000000 2 0
313						       59500000 650000000 3 0
314						       54500000 600000000 0 1
315						       49500000 550000000 1 1
316						       44500000 500000000 2 1
317						       40000000 450000000 3 1>;
318		};
319	
320	Required properties for plldiv clocks (plldiv = pll / 2):
321	- #clock-cells : from common clock binding; shall be set to 0.
322	- clocks : shall be the plla clock phandle.
323	
324	The pll divisor is equal to 2 and cannot be changed.
325	
326	For example:
327		plladiv: plladivck {
328			compatible = "atmel,at91sam9x5-clk-plldiv";
329			#clock-cells = <0>;
330			clocks = <&plla>;
331		};
332	
333	Required properties for programmable clocks:
334	- interrupt-parent : must reference the PMC node.
335	- #size-cells : shall be 0 (reg is used to encode clk id).
336	- #address-cells : shall be 1 (reg is used to encode clk id).
337	- clocks : shall be the programmable clock source phandles.
338		e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
339	- name: device tree node describing a specific prog clock.
340		* #clock-cells : from common clock binding; shall be set to 0.
341		* reg : programmable clock id (register offset from  PCKx
342				 register).
343		* interrupts : shall be set to "<(8 + id)>".
344	
345	For example:
346		prog: progck {
347			compatible = "atmel,at91sam9g45-clk-programmable";
348			#size-cells = <0>;
349			#address-cells = <1>;
350			interrupt-parent = <&pmc>;
351			clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
352	
353			prog0 {
354				#clock-cells = <0>;
355				reg = <0>;
356				interrupts = <8>;
357			};
358	
359			prog1 {
360				#clock-cells = <0>;
361				reg = <1>;
362				interrupts = <9>;
363			};
364		};
365	
366	
367	Required properties for smd clock:
368	- #clock-cells : from common clock binding; shall be set to 0.
369	- clocks : shall be the smd clock source phandles.
370		e.g. clocks = <&plladiv>, <&utmi>;
371	
372	For example:
373		smd: smdck {
374			compatible = "atmel,at91sam9x5-clk-smd";
375			#clock-cells = <0>;
376			clocks = <&plladiv>, <&utmi>;
377		};
378	
379	Required properties for system clocks:
380	- #size-cells : shall be 0 (reg is used to encode clk id).
381	- #address-cells : shall be 1 (reg is used to encode clk id).
382	- name: device tree node describing a specific system clock.
383		* #clock-cells : from common clock binding; shall be set to 0.
384		* reg: system clock id (bit position in SCER/SCDR/SCSR registers).
385		      See Atmel's datasheet to get a full list of system clock ids.
386	
387	For example:
388		system: systemck {
389			compatible = "atmel,at91rm9200-clk-system";
390			#address-cells = <1>;
391			#size-cells = <0>;
392	
393			ddrck {
394				#clock-cells = <0>;
395				reg = <2>;
396				clocks = <&mck>;
397			};
398	
399			uhpck {
400				#clock-cells = <0>;
401				reg = <6>;
402				clocks = <&usb>;
403			};
404	
405			udpck {
406				#clock-cells = <0>;
407				reg = <7>;
408				clocks = <&usb>;
409			};
410		};
411	
412	
413	Required properties for usb clock:
414	- #clock-cells : from common clock binding; shall be set to 0.
415	- clocks : shall be the smd clock source phandles.
416		e.g. clocks = <&pllb>;
417	- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
418		usb clock divisor table.
419		e.g. divisors = <1 2 4 0>;
420	
421	For example:
422		usb: usbck {
423			compatible = "atmel,at91sam9x5-clk-usb";
424			#clock-cells = <0>;
425			clocks = <&plladiv>, <&utmi>;
426		};
427	
428		usb: usbck {
429			compatible = "atmel,at91rm9200-clk-usb";
430			#clock-cells = <0>;
431			clocks = <&pllb>;
432			atmel,clk-divisors = <1 2 4 0>;
433		};
434	
435	
436	Required properties for utmi clock:
437	- interrupt-parent : must reference the PMC node.
438	- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
439	- #clock-cells : from common clock binding; shall be set to 0.
440	- clocks : shall be the main clock source phandle.
441	
442	For example:
443		utmi: utmick {
444			compatible = "atmel,at91sam9x5-clk-utmi";
445			interrupt-parent = <&pmc>;
446			interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
447			#clock-cells = <0>;
448			clocks = <&main>;
449		};
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