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Documentation / devicetree / bindings / clock / exynos5420-clock.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:00 EST.

1	* Samsung Exynos5420 Clock Controller
2	
3	The Exynos5420 clock controller generates and supplies clock to various
4	controllers within the Exynos5420 SoC.
5	
6	Required Properties:
7	
8	- compatible: should be one of the following.
9	  - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10	
11	- reg: physical base address of the controller and length of memory mapped
12	  region.
13	
14	- #clock-cells: should be 1.
15	
16	The following is the list of clocks generated by the controller. Each clock is
17	assigned an identifier and client nodes use this identifier to specify the
18	clock which they consume.
19	
20	
21	       [Core Clocks]
22	
23	  Clock			ID
24	  ----------------------------
25	
26	  fin_pll		1
27	
28	  [Clock Gate for Special Clocks]
29	
30	  Clock			ID
31	  ----------------------------
32	  sclk_uart0		128
33	  sclk_uart1		129
34	  sclk_uart2		130
35	  sclk_uart3		131
36	  sclk_mmc0		132
37	  sclk_mmc1		133
38	  sclk_mmc2		134
39	  sclk_spi0		135
40	  sclk_spi1		136
41	  sclk_spi2		137
42	  sclk_i2s1		138
43	  sclk_i2s2		139
44	  sclk_pcm1		140
45	  sclk_pcm2		141
46	  sclk_spdif		142
47	  sclk_hdmi		143
48	  sclk_pixel		144
49	  sclk_dp1		145
50	  sclk_mipi1		146
51	  sclk_fimd1		147
52	  sclk_maudio0		148
53	  sclk_maupcm0		149
54	  sclk_usbd300		150
55	  sclk_usbd301		151
56	  sclk_usbphy300	152
57	  sclk_usbphy301	153
58	  sclk_unipro		154
59	  sclk_pwm		155
60	  sclk_gscl_wa		156
61	  sclk_gscl_wb		157
62	  sclk_hdmiphy		158
63	
64	   [Peripheral Clock Gates]
65	
66	  Clock			ID
67	  ----------------------------
68	
69	  aclk66_peric		256
70	  uart0			257
71	  uart1			258
72	  uart2			259
73	  uart3			260
74	  i2c0			261
75	  i2c1			262
76	  i2c2			263
77	  i2c3			264
78	  i2c4			265
79	  i2c5			266
80	  i2c6			267
81	  i2c7			268
82	  i2c_hdmi		269
83	  tsadc			270
84	  spi0			271
85	  spi1			272
86	  spi2			273
87	  keyif			274
88	  i2s1			275
89	  i2s2			276
90	  pcm1			277
91	  pcm2			278
92	  pwm			279
93	  spdif			280
94	  i2c8			281
95	  i2c9			282
96	  i2c10			283
97	  aclk66_psgen		300
98	  chipid		301
99	  sysreg		302
100	  tzpc0			303
101	  tzpc1			304
102	  tzpc2			305
103	  tzpc3			306
104	  tzpc4			307
105	  tzpc5			308
106	  tzpc6			309
107	  tzpc7			310
108	  tzpc8			311
109	  tzpc9			312
110	  hdmi_cec		313
111	  seckey		314
112	  mct			315
113	  wdt			316
114	  rtc			317
115	  tmu			318
116	  tmu_gpu		319
117	  pclk66_gpio		330
118	  aclk200_fsys2		350
119	  mmc0			351
120	  mmc1			352
121	  mmc2			353
122	  sromc			354
123	  ufs			355
124	  aclk200_fsys		360
125	  tsi			361
126	  pdma0			362
127	  pdma1			363
128	  rtic			364
129	  usbh20		365
130	  usbd300		366
131	  usbd301		377
132	  aclk400_mscl		380
133	  mscl0			381
134	  mscl1			382
135	  mscl2			383
136	  smmu_mscl0		384
137	  smmu_mscl1		385
138	  smmu_mscl2		386
139	  aclk333		400
140	  mfc			401
141	  smmu_mfcl		402
142	  smmu_mfcr		403
143	  aclk200_disp1		410
144	  dsim1			411
145	  dp1			412
146	  hdmi			413
147	  aclk300_disp1		420
148	  fimd1			421
149	  smmu_fimd1		422
150	  aclk166		430
151	  mixer			431
152	  aclk266		440
153	  rotator		441
154	  mdma1			442
155	  smmu_rotator		443
156	  smmu_mdma1		444
157	  aclk300_jpeg		450
158	  jpeg			451
159	  jpeg2			452
160	  smmu_jpeg		453
161	  aclk300_gscl		460
162	  smmu_gscl0		461
163	  smmu_gscl1		462
164	  gscl_wa		463
165	  gscl_wb		464
166	  gscl0			465
167	  gscl1			466
168	  clk_3aa		467
169	  aclk266_g2d		470
170	  sss			471
171	  slim_sss		472
172	  mdma0			473
173	  aclk333_g2d		480
174	  g2d			481
175	  aclk333_432_gscl	490
176	  smmu_3aa		491
177	  smmu_fimcl0		492
178	  smmu_fimcl1		493
179	  smmu_fimcl3		494
180	  fimc_lite3		495
181	  aclk_g3d		500
182	  g3d			501
183	  smmu_mixer		502
184	
185	  Mux			ID
186	  ----------------------------
187	
188	  mout_hdmi		640
189	
190	  Divider		ID
191	  ----------------------------
192	
193	  dout_pixel		768
194	
195	Example 1: An example of a clock controller node is listed below.
196	
197		clock: clock-controller@0x10010000 {
198			compatible = "samsung,exynos5420-clock";
199			reg = <0x10010000 0x30000>;
200			#clock-cells = <1>;
201		};
202	
203	Example 2: UART controller node that consumes the clock generated by the clock
204		   controller. Refer to the standard clock bindings for information
205		   about 'clocks' and 'clock-names' property.
206	
207		serial@13820000 {
208			compatible = "samsung,exynos4210-uart";
209			reg = <0x13820000 0x100>;
210			interrupts = <0 54 0>;
211			clocks = <&clock 259>, <&clock 130>;
212			clock-names = "uart", "clk_uart_baud0";
213		};
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