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Documentation / devicetree / bindings / clock / imx31-clock.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	* Clock bindings for Freescale i.MX31
2	
3	Required properties:
4	- compatible: Should be "fsl,imx31-ccm"
5	- reg: Address and length of the register set
6	- interrupts: Should contain CCM interrupt
7	- #clock-cells: Should be <1>
8	
9	The clock consumer should specify the desired clock by having the clock
10	ID in its "clocks" phandle cell.  The following is a full list of i.MX31
11	clocks and IDs.
12	
13		Clock		    ID
14		-----------------------
15		dummy	             0
16		ckih                 1
17		ckil                 2
18		mpll                 3
19		spll                 4
20		upll                 5
21		mcu_main             6
22		hsp                  7
23		ahb                  8
24		nfc                  9
25		ipg                  10
26		per_div              11
27		per                  12
28		csi_sel              13
29		fir_sel              14
30		csi_div              15
31		usb_div_pre          16
32		usb_div_post         17
33		fir_div_pre          18
34		fir_div_post         19
35		sdhc1_gate           20
36		sdhc2_gate           21
37		gpt_gate             22
38		epit1_gate           23
39		epit2_gate           24
40		iim_gate             25
41		ata_gate             26
42		sdma_gate            27
43		cspi3_gate           28
44		rng_gate             29
45		uart1_gate           30
46		uart2_gate           31
47		ssi1_gate            32
48		i2c1_gate            33
49		i2c2_gate            34
50		i2c3_gate            35
51		hantro_gate          36
52		mstick1_gate         37
53		mstick2_gate         38
54		csi_gate             39
55		rtc_gate             40
56		wdog_gate            41
57		pwm_gate             42
58		sim_gate             43
59		ect_gate             44
60		usb_gate             45
61		kpp_gate             46
62		ipu_gate             47
63		uart3_gate           48
64		uart4_gate           49
65		uart5_gate           50
66		owire_gate           51
67		ssi2_gate            52
68		cspi1_gate           53
69		cspi2_gate           54
70		gacc_gate            55
71		emi_gate             56
72		rtic_gate            57
73		firi_gate            58
74	
75	Examples:
76	
77	clks: ccm@53f80000{
78		compatible = "fsl,imx31-ccm";
79		reg = <0x53f80000 0x4000>;
80		interrupts = <0 31 0x04 0 53 0x04>;
81		#clock-cells = <1>;
82	};
83	
84	uart1: serial@43f90000 {
85		compatible = "fsl,imx31-uart", "fsl,imx21-uart";
86		reg = <0x43f90000 0x4000>;
87		interrupts = <45>;
88		clocks = <&clks 10>, <&clks 30>;
89		clock-names = "ipg", "per";
90		status = "disabled";
91	};
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