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Documentation / devicetree / bindings / clock / keystone-pll.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	Status: Unstable - ABI compatibility may be broken in the future
2	
3	Binding for keystone PLLs. The main PLL IP typically has a multiplier,
4	a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
5	and PAPLL are controlled by the memory mapped register where as the Main
6	PLL is controlled by a PLL controller registers along with memory mapped
7	registers.
8	
9	This binding uses the common clock binding[1].
10	
11	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12	
13	Required properties:
14	- #clock-cells : from common clock binding; shall be set to 0.
15	- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16	- clocks : parent clock phandle
17	- reg - pll control0 and pll multipler registers
18	- reg-names : control and multiplier. The multiplier is applicable only for
19			main pll clock
20	- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
21			for postdiv
22	
23	Example:
24		mainpllclk: mainpllclk@2310110 {
25			#clock-cells = <0>;
26			compatible = "ti,keystone,main-pll-clock";
27			clocks = <&refclksys>;
28			reg = <0x02620350 4>, <0x02310110 4>;
29			reg-names = "control", "multiplier";
30			fixed-postdiv = <2>;
31		};
32	
33		papllclk: papllclk@2620358 {
34			#clock-cells = <0>;
35			compatible = "ti,keystone,pll-clock";
36			clocks = <&refclkpass>;
37			clock-output-names = "pa-pll-clk";
38			reg = <0x02620358 4>;
39			reg-names = "control";
40		};
41	
42	Required properties:
43	- #clock-cells : from common clock binding; shall be set to 0.
44	- compatible : shall be "ti,keystone,pll-mux-clock"
45	- clocks : link phandles of parent clocks
46	- reg - pll mux register
47	- bit-shift : number of bits to shift the bit-mask
48	- bit-mask : arbitrary bitmask for programming the mux
49	
50	Optional properties:
51	- clock-output-names : From common clock binding.
52	
53	Example:
54		mainmuxclk: mainmuxclk@2310108 {
55			#clock-cells = <0>;
56			compatible = "ti,keystone,pll-mux-clock";
57			clocks = <&mainpllclk>, <&refclkmain>;
58			reg = <0x02310108 4>;
59			bit-shift = <23>;
60			bit-mask = <1>;
61			clock-output-names = "mainmuxclk";
62		};
63	
64	Required properties:
65	- #clock-cells : from common clock binding; shall be set to 0.
66	- compatible : shall be "ti,keystone,pll-divider-clock"
67	- clocks : parent clock phandle
68	- reg - pll mux register
69	- bit-shift : number of bits to shift the bit-mask
70	- bit-mask : arbitrary bitmask for programming the divider
71	
72	Optional properties:
73	- clock-output-names : From common clock binding.
74	
75	Example:
76		gemtraceclk: gemtraceclk@2310120 {
77			#clock-cells = <0>;
78			compatible = "ti,keystone,pll-divider-clock";
79			clocks = <&mainmuxclk>;
80			reg = <0x02310120 4>;
81			bit-shift = <0>;
82			bit-mask = <8>;
83			clock-output-names = "gemtraceclk";
84		};
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