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Documentation / devicetree / bindings / clock / mvebu-core-clock.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:00 EST.

1	* Core Clock bindings for Marvell MVEBU SoCs
2	
3	Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4	reading the Sample-At-Reset (SAR) register. The core clock consumer should
5	specify the desired clock by having the clock ID in its "clocks" phandle cell.
6	
7	The following is a list of provided IDs and clock names on Armada 370/XP:
8	 0 = tclk    (Internal Bus clock)
9	 1 = cpuclk  (CPU clock)
10	 2 = nbclk   (L2 Cache clock)
11	 3 = hclk    (DRAM control clock)
12	 4 = dramclk (DDR clock)
13	
14	The following is a list of provided IDs and clock names on Kirkwood and Dove:
15	 0 = tclk   (Internal Bus clock)
16	 1 = cpuclk (CPU0 clock)
17	 2 = l2clk  (L2 Cache clock derived from CPU0 clock)
18	 3 = ddrclk (DDR controller clock derived from CPU0 clock)
19	
20	Required properties:
21	- compatible : shall be one of the following:
22		"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
23		"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
24		"marvell,dove-core-clock" - for Dove SoC core clocks
25		"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
26		"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
27	- reg : shall be the register address of the Sample-At-Reset (SAR) register
28	- #clock-cells : from common clock binding; shall be set to 1
29	
30	Optional properties:
31	- clock-output-names : from common clock binding; allows overwrite default clock
32		output names ("tclk", "cpuclk", "l2clk", "ddrclk")
33	
34	Example:
35	
36	core_clk: core-clocks@d0214 {
37		compatible = "marvell,dove-core-clock";
38		reg = <0xd0214 0x4>;
39		#clock-cells = <1>;
40	};
41	
42	spi0: spi@10600 {
43		compatible = "marvell,orion-spi";
44		/* ... */
45		/* get tclk from core clock provider */
46		clocks = <&core_clk 0>;
47	};
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