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Documentation / devicetree / bindings / clock / renesas,cpg-div6-clocks.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	* Renesas CPG DIV6 Clock
2	
3	The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
4	Generator (CPG). They clock input is divided by a configurable factor from 1
5	to 64.
6	
7	Required Properties:
8	
9	  - compatible: Must be one of the following
10	    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
11	    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
12	    - "renesas,cpg-div6-clock" for generic DIV6 clocks
13	  - reg: Base address and length of the memory resource used by the DIV6 clock
14	  - clocks: Reference to the parent clock
15	  - #clock-cells: Must be 0
16	  - clock-output-names: The name of the clock as a free-form string
17	
18	
19	Example
20	-------
21	
22		sd2_clk: sd2_clk@e6150078 {
23			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
24			reg = <0 0xe6150078 0 4>;
25			clocks = <&pll1_div2_clk>;
26			#clock-cells = <0>;
27			clock-output-names = "sd2";
28		};
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