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Documentation / devicetree / bindings / clock / renesas,rz-cpg-clocks.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	* Renesas RZ Clock Pulse Generator (CPG)
2	
3	The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
4	CPU and GPU clocks, and several fixed ratio dividers.
5	
6	Required Properties:
7	
8	  - compatible: Must be one of
9	    - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
10	    - "renesas,rz-cpg-clocks" for the generic RZ CPG
11	  - reg: Base address and length of the memory resource used by the CPG
12	  - clocks: References to possible parent clocks. Order must match clock modes
13	    in the datasheet. For the r7s72100, this is extal, usb_x1.
14	  - #clock-cells: Must be 1
15	  - clock-output-names: The names of the clocks. Supported clocks are "pll",
16	    "i", and "g"
17	
18	
19	Example
20	-------
21	
22		cpg_clocks: cpg_clocks@fcfe0000 {
23			#clock-cells = <1>;
24			compatible = "renesas,r7s72100-cpg-clocks",
25				     "renesas,rz-cpg-clocks";
26			reg = <0xfcfe0000 0x18>;
27			clocks = <&extal_clk>, <&usb_x1_clk>;
28			clock-output-names = "pll", "i", "g";
29		};
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