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Documentation / devicetree / bindings / clock / sunxi.txt




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Based on kernel version 4.1. Page generated on 2015-06-28 12:08 EST.

1	Device Tree Clock bindings for arch-sunxi
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10		"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11		"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12		"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13		"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
14		"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
15		"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
16		"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17		"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
18		"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
19		"allwinner,sun4i-a10-axi-clk" - for the AXI clock
20		"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
21		"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
22		"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
23		"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
24		"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
25		"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
26		"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
27		"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
28		"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
29		"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
30		"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
31		"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
32		"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
33		"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
34		"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
35		"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
36		"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
37		"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
38		"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
39		"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
40		"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
41		"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
42		"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
43		"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
44		"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
45		"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
46		"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
47		"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
48		"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
49		"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
50		"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
51		"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
52		"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
53		"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
54		"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
55		"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
56		"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
57		"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
58		"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
59		"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
60		"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
61		"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
62		"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
63		"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
64		"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
65		"allwinner,sun7i-a20-out-clk" - for the external output clocks
66		"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
67		"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
68		"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
69		"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
70		"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
71		"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
72	
73	Required properties for all clocks:
74	- reg : shall be the control register address for the clock.
75	- clocks : shall be the input parent clock(s) phandle for the clock. For
76		multiplexed clocks, the list order must match the hardware
77		programming order.
78	- #clock-cells : from common clock binding; shall be set to 0 except for
79		the following compatibles where it shall be set to 1:
80		"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
81		"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
82		"allwinner,*-usb-clk", "allwinner,*-mmc-clk",
83		"allwinner,*-mmc-config-clk"
84	- clock-output-names : shall be the corresponding names of the outputs.
85		If the clock module only has one output, the name shall be the
86		module name.
87	
88	And "allwinner,*-usb-clk" clocks also require:
89	- reset-cells : shall be set to 1
90	
91	The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
92	- #reset-cells : shall be set to 1
93	- resets : shall be the reset control phandle for the mmc block.
94	
95	For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
96	dummy clocks at 25 MHz and 125 MHz, respectively. See example.
97	
98	Clock consumers should specify the desired clocks they use with a
99	"clocks" phandle cell. Consumers that are using a gated clock should
100	provide an additional ID in their clock property. This ID is the
101	offset of the bit controlling this particular gate in the register.
102	For the other clocks with "#clock-cells" = 1, the additional ID shall
103	refer to the index of the output.
104	
105	For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
106	is the normal PLL6 output, or "pll6". The second output is rate doubled
107	PLL6, or "pll6x2".
108	
109	The "allwinner,*-mmc-clk" clocks have three different outputs: the
110	main clock, with the ID 0, and the output and sample clocks, with the
111	IDs 1 and 2, respectively.
112	
113	The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
114	per mmc controller. The number of outputs is determined by the size of
115	the address block, which is related to the overall mmc block.
116	
117	For example:
118	
119	osc24M: clk@01c20050 {
120		#clock-cells = <0>;
121		compatible = "allwinner,sun4i-a10-osc-clk";
122		reg = <0x01c20050 0x4>;
123		clocks = <&osc24M_fixed>;
124		clock-output-names = "osc24M";
125	};
126	
127	pll1: clk@01c20000 {
128		#clock-cells = <0>;
129		compatible = "allwinner,sun4i-a10-pll1-clk";
130		reg = <0x01c20000 0x4>;
131		clocks = <&osc24M>;
132		clock-output-names = "pll1";
133	};
134	
135	pll5: clk@01c20020 {
136		#clock-cells = <1>;
137		compatible = "allwinner,sun4i-pll5-clk";
138		reg = <0x01c20020 0x4>;
139		clocks = <&osc24M>;
140		clock-output-names = "pll5_ddr", "pll5_other";
141	};
142	
143	pll6: clk@01c20028 {
144		#clock-cells = <1>;
145		compatible = "allwinner,sun6i-a31-pll6-clk";
146		reg = <0x01c20028 0x4>;
147		clocks = <&osc24M>;
148		clock-output-names = "pll6", "pll6x2";
149	};
150	
151	cpu: cpu@01c20054 {
152		#clock-cells = <0>;
153		compatible = "allwinner,sun4i-a10-cpu-clk";
154		reg = <0x01c20054 0x4>;
155		clocks = <&osc32k>, <&osc24M>, <&pll1>;
156		clock-output-names = "cpu";
157	};
158	
159	mmc0_clk: clk@01c20088 {
160		#clock-cells = <1>;
161		compatible = "allwinner,sun4i-a10-mmc-clk";
162		reg = <0x01c20088 0x4>;
163		clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
164		clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
165	};
166	
167	mii_phy_tx_clk: clk@2 {
168		#clock-cells = <0>;
169		compatible = "fixed-clock";
170		clock-frequency = <25000000>;
171		clock-output-names = "mii_phy_tx";
172	};
173	
174	gmac_int_tx_clk: clk@3 {
175		#clock-cells = <0>;
176		compatible = "fixed-clock";
177		clock-frequency = <125000000>;
178		clock-output-names = "gmac_int_tx";
179	};
180	
181	gmac_clk: clk@01c20164 {
182		#clock-cells = <0>;
183		compatible = "allwinner,sun7i-a20-gmac-clk";
184		reg = <0x01c20164 0x4>;
185		/*
186		 * The first clock must be fixed at 25MHz;
187		 * the second clock must be fixed at 125MHz
188		 */
189		clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
190		clock-output-names = "gmac";
191	};
192	
193	mmc_config_clk: clk@01c13000 {
194		compatible = "allwinner,sun9i-a80-mmc-config-clk";
195		reg = <0x01c13000 0x10>;
196		clocks = <&ahb0_gates 8>;
197		clock-names = "ahb";
198		resets = <&ahb0_resets 8>;
199		reset-names = "ahb";
200		#clock-cells = <1>;
201		#reset-cells = <1>;
202		clock-output-names = "mmc0_config", "mmc1_config",
203				     "mmc2_config", "mmc3_config";
204	};
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