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Documentation / devicetree / bindings / clock / sunxi.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	Device Tree Clock bindings for arch-sunxi
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10		"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11		"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12		"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
13		"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
14		"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
15		"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
16		"allwinner,sun4i-a10-axi-clk" - for the AXI clock
17		"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
18		"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
19		"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
20		"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
21		"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
22		"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
23		"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
24		"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
25		"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
26		"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
27		"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
28		"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
29		"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
30		"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
31		"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
32		"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
33		"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
34		"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
35		"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
36		"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
37		"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
38		"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
39		"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
40		"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
41		"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
42		"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
43		"allwinner,sun7i-a20-out-clk" - for the external output clocks
44		"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
45		"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
46		"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
47		"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
48	
49	Required properties for all clocks:
50	- reg : shall be the control register address for the clock.
51	- clocks : shall be the input parent clock(s) phandle for the clock. For
52		multiplexed clocks, the list order must match the hardware
53		programming order.
54	- #clock-cells : from common clock binding; shall be set to 0 except for
55		"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
56		"allwinner,sun4i-pll6-clk" where it shall be set to 1
57	- clock-output-names : shall be the corresponding names of the outputs.
58		If the clock module only has one output, the name shall be the
59		module name.
60	
61	And "allwinner,*-usb-clk" clocks also require:
62	- reset-cells : shall be set to 1
63	
64	For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
65	dummy clocks at 25 MHz and 125 MHz, respectively. See example.
66	
67	Clock consumers should specify the desired clocks they use with a
68	"clocks" phandle cell. Consumers that are using a gated clock should
69	provide an additional ID in their clock property. This ID is the
70	offset of the bit controlling this particular gate in the register.
71	
72	For example:
73	
74	osc24M: clk@01c20050 {
75		#clock-cells = <0>;
76		compatible = "allwinner,sun4i-a10-osc-clk";
77		reg = <0x01c20050 0x4>;
78		clocks = <&osc24M_fixed>;
79		clock-output-names = "osc24M";
80	};
81	
82	pll1: clk@01c20000 {
83		#clock-cells = <0>;
84		compatible = "allwinner,sun4i-a10-pll1-clk";
85		reg = <0x01c20000 0x4>;
86		clocks = <&osc24M>;
87		clock-output-names = "pll1";
88	};
89	
90	pll5: clk@01c20020 {
91		#clock-cells = <1>;
92		compatible = "allwinner,sun4i-pll5-clk";
93		reg = <0x01c20020 0x4>;
94		clocks = <&osc24M>;
95		clock-output-names = "pll5_ddr", "pll5_other";
96	};
97	
98	cpu: cpu@01c20054 {
99		#clock-cells = <0>;
100		compatible = "allwinner,sun4i-a10-cpu-clk";
101		reg = <0x01c20054 0x4>;
102		clocks = <&osc32k>, <&osc24M>, <&pll1>;
103		clock-output-names = "cpu";
104	};
105	
106	mmc0_clk: clk@01c20088 {
107		#clock-cells = <0>;
108		compatible = "allwinner,sun4i-mod0-clk";
109		reg = <0x01c20088 0x4>;
110		clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
111		clock-output-names = "mmc0";
112	};
113	
114	mii_phy_tx_clk: clk@2 {
115		#clock-cells = <0>;
116		compatible = "fixed-clock";
117		clock-frequency = <25000000>;
118		clock-output-names = "mii_phy_tx";
119	};
120	
121	gmac_int_tx_clk: clk@3 {
122		#clock-cells = <0>;
123		compatible = "fixed-clock";
124		clock-frequency = <125000000>;
125		clock-output-names = "gmac_int_tx";
126	};
127	
128	gmac_clk: clk@01c20164 {
129		#clock-cells = <0>;
130		compatible = "allwinner,sun7i-a20-gmac-clk";
131		reg = <0x01c20164 0x4>;
132		/*
133		 * The first clock must be fixed at 25MHz;
134		 * the second clock must be fixed at 125MHz
135		 */
136		clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
137		clock-output-names = "gmac";
138	};
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