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Documentation / devicetree / bindings / clock / sunxi.txt




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Based on kernel version 4.0. Page generated on 2015-04-14 21:20 EST.

1	Device Tree Clock bindings for arch-sunxi
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10		"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11		"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12		"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13		"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
14		"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
15		"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
16		"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17		"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
18		"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
19		"allwinner,sun4i-a10-axi-clk" - for the AXI clock
20		"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
21		"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
22		"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
23		"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
24		"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
25		"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
26		"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
27		"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
28		"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
29		"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
30		"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
31		"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
32		"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
33		"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
34		"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
35		"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
36		"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
37		"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
38		"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
39		"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
40		"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
41		"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
42		"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
43		"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
44		"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
45		"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
46		"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
47		"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
48		"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
49		"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
50		"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
51		"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
52		"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
53		"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
54		"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
55		"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
56		"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
57		"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
58		"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
59		"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
60		"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
61		"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
62		"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
63		"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
64		"allwinner,sun7i-a20-out-clk" - for the external output clocks
65		"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
66		"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
67		"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
68		"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
69	
70	Required properties for all clocks:
71	- reg : shall be the control register address for the clock.
72	- clocks : shall be the input parent clock(s) phandle for the clock. For
73		multiplexed clocks, the list order must match the hardware
74		programming order.
75	- #clock-cells : from common clock binding; shall be set to 0 except for
76		the following compatibles where it shall be set to 1:
77		"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
78		"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
79		"allwinner,*-usb-clk", "allwinner,*-mmc-clk",
80		"allwinner,*-mmc-config-clk"
81	- clock-output-names : shall be the corresponding names of the outputs.
82		If the clock module only has one output, the name shall be the
83		module name.
84	
85	And "allwinner,*-usb-clk" clocks also require:
86	- reset-cells : shall be set to 1
87	
88	The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
89	- #reset-cells : shall be set to 1
90	- resets : shall be the reset control phandle for the mmc block.
91	
92	For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
93	dummy clocks at 25 MHz and 125 MHz, respectively. See example.
94	
95	Clock consumers should specify the desired clocks they use with a
96	"clocks" phandle cell. Consumers that are using a gated clock should
97	provide an additional ID in their clock property. This ID is the
98	offset of the bit controlling this particular gate in the register.
99	For the other clocks with "#clock-cells" = 1, the additional ID shall
100	refer to the index of the output.
101	
102	For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
103	is the normal PLL6 output, or "pll6". The second output is rate doubled
104	PLL6, or "pll6x2".
105	
106	The "allwinner,*-mmc-clk" clocks have three different outputs: the
107	main clock, with the ID 0, and the output and sample clocks, with the
108	IDs 1 and 2, respectively.
109	
110	The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
111	per mmc controller. The number of outputs is determined by the size of
112	the address block, which is related to the overall mmc block.
113	
114	For example:
115	
116	osc24M: clk@01c20050 {
117		#clock-cells = <0>;
118		compatible = "allwinner,sun4i-a10-osc-clk";
119		reg = <0x01c20050 0x4>;
120		clocks = <&osc24M_fixed>;
121		clock-output-names = "osc24M";
122	};
123	
124	pll1: clk@01c20000 {
125		#clock-cells = <0>;
126		compatible = "allwinner,sun4i-a10-pll1-clk";
127		reg = <0x01c20000 0x4>;
128		clocks = <&osc24M>;
129		clock-output-names = "pll1";
130	};
131	
132	pll5: clk@01c20020 {
133		#clock-cells = <1>;
134		compatible = "allwinner,sun4i-pll5-clk";
135		reg = <0x01c20020 0x4>;
136		clocks = <&osc24M>;
137		clock-output-names = "pll5_ddr", "pll5_other";
138	};
139	
140	pll6: clk@01c20028 {
141		#clock-cells = <1>;
142		compatible = "allwinner,sun6i-a31-pll6-clk";
143		reg = <0x01c20028 0x4>;
144		clocks = <&osc24M>;
145		clock-output-names = "pll6", "pll6x2";
146	};
147	
148	cpu: cpu@01c20054 {
149		#clock-cells = <0>;
150		compatible = "allwinner,sun4i-a10-cpu-clk";
151		reg = <0x01c20054 0x4>;
152		clocks = <&osc32k>, <&osc24M>, <&pll1>;
153		clock-output-names = "cpu";
154	};
155	
156	mmc0_clk: clk@01c20088 {
157		#clock-cells = <1>;
158		compatible = "allwinner,sun4i-a10-mmc-clk";
159		reg = <0x01c20088 0x4>;
160		clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
161		clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
162	};
163	
164	mii_phy_tx_clk: clk@2 {
165		#clock-cells = <0>;
166		compatible = "fixed-clock";
167		clock-frequency = <25000000>;
168		clock-output-names = "mii_phy_tx";
169	};
170	
171	gmac_int_tx_clk: clk@3 {
172		#clock-cells = <0>;
173		compatible = "fixed-clock";
174		clock-frequency = <125000000>;
175		clock-output-names = "gmac_int_tx";
176	};
177	
178	gmac_clk: clk@01c20164 {
179		#clock-cells = <0>;
180		compatible = "allwinner,sun7i-a20-gmac-clk";
181		reg = <0x01c20164 0x4>;
182		/*
183		 * The first clock must be fixed at 25MHz;
184		 * the second clock must be fixed at 125MHz
185		 */
186		clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
187		clock-output-names = "gmac";
188	};
189	
190	mmc_config_clk: clk@01c13000 {
191		compatible = "allwinner,sun9i-a80-mmc-config-clk";
192		reg = <0x01c13000 0x10>;
193		clocks = <&ahb0_gates 8>;
194		clock-names = "ahb";
195		resets = <&ahb0_resets 8>;
196		reset-names = "ahb";
197		#clock-cells = <1>;
198		#reset-cells = <1>;
199		clock-output-names = "mmc0_config", "mmc1_config",
200				     "mmc2_config", "mmc3_config";
201	};
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