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Documentation / devicetree / bindings / clock / sunxi.txt




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Based on kernel version 4.7.2. Page generated on 2016-08-22 22:40 EST.

1	Device Tree Clock bindings for arch-sunxi
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10		"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11		"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12		"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13		"allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
14		"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
15		"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
16		"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
17		"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
18		"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
19		"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
20		"allwinner,sun4i-a10-axi-clk" - for the AXI clock
21		"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
22		"allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs
23		"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
24		"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
25		"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
26		"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
27		"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
28		"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
29		"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
30		"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
31		"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
32		"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
33		"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
34		"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
35		"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
36		"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
37		"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
38		"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
39		"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
40		"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
41		"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
42		"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
43		"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
44		"allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
45		"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
46		"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
47		"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
48		"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
49		"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
50		"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
51		"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
52		"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
53		"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
54		"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
55		"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
56		"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
57		"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
58		"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
59		"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
60		"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
61		"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
62		"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
63		"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
64		"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
65		"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
66		"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
67		"allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
68		"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
69		"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
70		"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
71		"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
72		"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
73		"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
74		"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
75		"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
76		"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
77		"allwinner,sun7i-a20-out-clk" - for the external output clocks
78		"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
79		"allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10
80		"allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10
81		"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
82		"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
83		"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
84		"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
85		"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
86		"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
87		"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
88		"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
89		"allwinner,sun6i-a31-display-clk" - for the display clocks
90	
91	Required properties for all clocks:
92	- reg : shall be the control register address for the clock.
93	- clocks : shall be the input parent clock(s) phandle for the clock. For
94		multiplexed clocks, the list order must match the hardware
95		programming order.
96	- #clock-cells : from common clock binding; shall be set to 0 except for
97		the following compatibles where it shall be set to 1:
98		"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
99		"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
100		"allwinner,*-usb-clk", "allwinner,*-mmc-clk",
101		"allwinner,*-mmc-config-clk"
102	- clock-output-names : shall be the corresponding names of the outputs.
103		If the clock module only has one output, the name shall be the
104		module name.
105	
106	And "allwinner,*-usb-clk" clocks also require:
107	- reset-cells : shall be set to 1
108	
109	The "allwinner,sun4i-a10-ve-clk" clock also requires:
110	- reset-cells : shall be set to 0
111	
112	The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
113	- #reset-cells : shall be set to 1
114	- resets : shall be the reset control phandle for the mmc block.
115	
116	For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
117	dummy clocks at 25 MHz and 125 MHz, respectively. See example.
118	
119	Clock consumers should specify the desired clocks they use with a
120	"clocks" phandle cell. Consumers that are using a gated clock should
121	provide an additional ID in their clock property. This ID is the
122	offset of the bit controlling this particular gate in the register.
123	For the other clocks with "#clock-cells" = 1, the additional ID shall
124	refer to the index of the output.
125	
126	For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
127	is the normal PLL6 output, or "pll6". The second output is rate doubled
128	PLL6, or "pll6x2".
129	
130	The "allwinner,*-mmc-clk" clocks have three different outputs: the
131	main clock, with the ID 0, and the output and sample clocks, with the
132	IDs 1 and 2, respectively.
133	
134	The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
135	per mmc controller. The number of outputs is determined by the size of
136	the address block, which is related to the overall mmc block.
137	
138	For example:
139	
140	osc24M: clk@01c20050 {
141		#clock-cells = <0>;
142		compatible = "allwinner,sun4i-a10-osc-clk";
143		reg = <0x01c20050 0x4>;
144		clocks = <&osc24M_fixed>;
145		clock-output-names = "osc24M";
146	};
147	
148	pll1: clk@01c20000 {
149		#clock-cells = <0>;
150		compatible = "allwinner,sun4i-a10-pll1-clk";
151		reg = <0x01c20000 0x4>;
152		clocks = <&osc24M>;
153		clock-output-names = "pll1";
154	};
155	
156	pll5: clk@01c20020 {
157		#clock-cells = <1>;
158		compatible = "allwinner,sun4i-pll5-clk";
159		reg = <0x01c20020 0x4>;
160		clocks = <&osc24M>;
161		clock-output-names = "pll5_ddr", "pll5_other";
162	};
163	
164	pll6: clk@01c20028 {
165		#clock-cells = <1>;
166		compatible = "allwinner,sun6i-a31-pll6-clk";
167		reg = <0x01c20028 0x4>;
168		clocks = <&osc24M>;
169		clock-output-names = "pll6", "pll6x2";
170	};
171	
172	cpu: cpu@01c20054 {
173		#clock-cells = <0>;
174		compatible = "allwinner,sun4i-a10-cpu-clk";
175		reg = <0x01c20054 0x4>;
176		clocks = <&osc32k>, <&osc24M>, <&pll1>;
177		clock-output-names = "cpu";
178	};
179	
180	mmc0_clk: clk@01c20088 {
181		#clock-cells = <1>;
182		compatible = "allwinner,sun4i-a10-mmc-clk";
183		reg = <0x01c20088 0x4>;
184		clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
185		clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
186	};
187	
188	mii_phy_tx_clk: clk@2 {
189		#clock-cells = <0>;
190		compatible = "fixed-clock";
191		clock-frequency = <25000000>;
192		clock-output-names = "mii_phy_tx";
193	};
194	
195	gmac_int_tx_clk: clk@3 {
196		#clock-cells = <0>;
197		compatible = "fixed-clock";
198		clock-frequency = <125000000>;
199		clock-output-names = "gmac_int_tx";
200	};
201	
202	gmac_clk: clk@01c20164 {
203		#clock-cells = <0>;
204		compatible = "allwinner,sun7i-a20-gmac-clk";
205		reg = <0x01c20164 0x4>;
206		/*
207		 * The first clock must be fixed at 25MHz;
208		 * the second clock must be fixed at 125MHz
209		 */
210		clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
211		clock-output-names = "gmac";
212	};
213	
214	mmc_config_clk: clk@01c13000 {
215		compatible = "allwinner,sun9i-a80-mmc-config-clk";
216		reg = <0x01c13000 0x10>;
217		clocks = <&ahb0_gates 8>;
218		clock-names = "ahb";
219		resets = <&ahb0_resets 8>;
220		reset-names = "ahb";
221		#clock-cells = <1>;
222		#reset-cells = <1>;
223		clock-output-names = "mmc0_config", "mmc1_config",
224				     "mmc2_config", "mmc3_config";
225	};
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