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Documentation / devicetree / bindings / clock / zynq-7000.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:00 EST.

1	Device Tree Clock bindings for the Zynq 7000 EPP
2	
3	The Zynq EPP has several different clk providers, each with there own bindings.
4	The purpose of this document is to document their usage.
5	
6	See clock_bindings.txt for more information on the generic clock bindings.
7	See Chapter 25 of Zynq TRM for more information about Zynq clocks.
8	
9	== Clock Controller ==
10	The clock controller is a logical abstraction of Zynq's clock tree. It reads
11	required input clock frequencies from the devicetree and acts as clock provider
12	for all clock consumers of PS clocks.
13	
14	Required properties:
15	 - #clock-cells : Must be 1
16	 - compatible : "xlnx,ps7-clkc"
17	 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
18			      (usually 33 MHz oscillators are used for Zynq platforms)
19	 - clock-output-names : List of strings used to name the clock outputs. Shall be
20				a list of the outputs given below.
21	
22	Optional properties:
23	 - clocks : as described in the clock bindings
24	 - clock-names : as described in the clock bindings
25	
26	Clock inputs:
27	The following strings are optional parameters to the 'clock-names' property in
28	order to provide an optional (E)MIO clock source.
29	 - swdt_ext_clk
30	 - gem0_emio_clk
31	 - gem1_emio_clk
32	 - mio_clk_XX		# with XX = 00..53
33	...
34	
35	Clock outputs:
36	 0:  armpll
37	 1:  ddrpll
38	 2:  iopll
39	 3:  cpu_6or4x
40	 4:  cpu_3or2x
41	 5:  cpu_2x
42	 6:  cpu_1x
43	 7:  ddr2x
44	 8:  ddr3x
45	 9:  dci
46	 10: lqspi
47	 11: smc
48	 12: pcap
49	 13: gem0
50	 14: gem1
51	 15: fclk0
52	 16: fclk1
53	 17: fclk2
54	 18: fclk3
55	 19: can0
56	 20: can1
57	 21: sdio0
58	 22: sdio1
59	 23: uart0
60	 24: uart1
61	 25: spi0
62	 26: spi1
63	 27: dma
64	 28: usb0_aper
65	 29: usb1_aper
66	 30: gem0_aper
67	 31: gem1_aper
68	 32: sdio0_aper
69	 33: sdio1_aper
70	 34: spi0_aper
71	 35: spi1_aper
72	 36: can0_aper
73	 37: can1_aper
74	 38: i2c0_aper
75	 39: i2c1_aper
76	 40: uart0_aper
77	 41: uart1_aper
78	 42: gpio_aper
79	 43: lqspi_aper
80	 44: smc_aper
81	 45: swdt
82	 46: dbg_trc
83	 47: dbg_apb
84	
85	Example:
86		clkc: clkc {
87			#clock-cells = <1>;
88			compatible = "xlnx,ps7-clkc";
89			ps-clk-frequency = <33333333>;
90			clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
91					"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
92					"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
93					"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
94					"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
95					"dma", "usb0_aper", "usb1_aper", "gem0_aper",
96					"gem1_aper", "sdio0_aper", "sdio1_aper",
97					"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
98					"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
99					"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
100					"dbg_trc", "dbg_apb";
101			# optional props
102			clocks = <&clkc 16>, <&clk_foo>;
103			clock-names = "gem1_emio_clk", "can_mio_clk_23";
104		};
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