Based on kernel version 3.17.3. Page generated on 2014-11-14 22:14 EST.
1 Generic CPU0 cpufreq driver 2 3 It is a generic cpufreq driver for CPU0 frequency management. It 4 supports both uniprocessor (UP) and symmetric multiprocessor (SMP) 5 systems which share clock and voltage across all CPUs. 6 7 Both required and optional properties listed below must be defined 8 under node /cpus/cpu@0. 9 10 Required properties: 11 - None 12 13 Optional properties: 14 - operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt for 15 details. OPPs *must* be supplied either via DT, i.e. this property, or 16 populated at runtime. 17 - clock-latency: Specify the possible maximum transition latency for clock, 18 in unit of nanoseconds. 19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage. 20 - #cooling-cells: 21 - cooling-min-level: 22 - cooling-max-level: 23 Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. 24 25 Examples: 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 compatible = "arm,cortex-a9"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 operating-points = < 36 /* kHz uV */ 37 792000 1100000 38 396000 950000 39 198000 850000 40 >; 41 clock-latency = <61036>; /* two CLK32 periods */ 42 #cooling-cells = <2>; 43 cooling-min-level = <0>; 44 cooling-max-level = <2>; 45 }; 46 47 cpu@1 { 48 compatible = "arm,cortex-a9"; 49 reg = <1>; 50 next-level-cache = <&L2>; 51 }; 52 53 cpu@2 { 54 compatible = "arm,cortex-a9"; 55 reg = <2>; 56 next-level-cache = <&L2>; 57 }; 58 59 cpu@3 { 60 compatible = "arm,cortex-a9"; 61 reg = <3>; 62 next-level-cache = <&L2>; 63 }; 64 };