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Documentation / devicetree / bindings / gpu / nvidia,tegra20-host1x.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:00 EST.

1	NVIDIA Tegra host1x
2	
3	Required properties:
4	- compatible: "nvidia,tegra<chip>-host1x"
5	- reg: Physical base address and length of the controller's registers.
6	- interrupts: The interrupt outputs from the controller.
7	- #address-cells: The number of cells used to represent physical base addresses
8	  in the host1x address space. Should be 1.
9	- #size-cells: The number of cells used to represent the size of an address
10	  range in the host1x address space. Should be 1.
11	- ranges: The mapping of the host1x address space to the CPU address space.
12	- clocks: Must contain one entry, for the module clock.
13	  See ../clocks/clock-bindings.txt for details.
14	- resets: Must contain an entry for each entry in reset-names.
15	  See ../reset/reset.txt for details.
16	- reset-names: Must include the following entries:
17	  - host1x
18	
19	The host1x top-level node defines a number of children, each representing one
20	of the following host1x client modules:
21	
22	- mpe: video encoder
23	
24	  Required properties:
25	  - compatible: "nvidia,tegra<chip>-mpe"
26	  - reg: Physical base address and length of the controller's registers.
27	  - interrupts: The interrupt outputs from the controller.
28	  - clocks: Must contain one entry, for the module clock.
29	    See ../clocks/clock-bindings.txt for details.
30	  - resets: Must contain an entry for each entry in reset-names.
31	    See ../reset/reset.txt for details.
32	  - reset-names: Must include the following entries:
33	    - mpe
34	
35	- vi: video input
36	
37	  Required properties:
38	  - compatible: "nvidia,tegra<chip>-vi"
39	  - reg: Physical base address and length of the controller's registers.
40	  - interrupts: The interrupt outputs from the controller.
41	  - clocks: Must contain one entry, for the module clock.
42	    See ../clocks/clock-bindings.txt for details.
43	  - resets: Must contain an entry for each entry in reset-names.
44	    See ../reset/reset.txt for details.
45	  - reset-names: Must include the following entries:
46	    - vi
47	
48	- epp: encoder pre-processor
49	
50	  Required properties:
51	  - compatible: "nvidia,tegra<chip>-epp"
52	  - reg: Physical base address and length of the controller's registers.
53	  - interrupts: The interrupt outputs from the controller.
54	  - clocks: Must contain one entry, for the module clock.
55	    See ../clocks/clock-bindings.txt for details.
56	  - resets: Must contain an entry for each entry in reset-names.
57	    See ../reset/reset.txt for details.
58	  - reset-names: Must include the following entries:
59	    - epp
60	
61	- isp: image signal processor
62	
63	  Required properties:
64	  - compatible: "nvidia,tegra<chip>-isp"
65	  - reg: Physical base address and length of the controller's registers.
66	  - interrupts: The interrupt outputs from the controller.
67	  - clocks: Must contain one entry, for the module clock.
68	    See ../clocks/clock-bindings.txt for details.
69	  - resets: Must contain an entry for each entry in reset-names.
70	    See ../reset/reset.txt for details.
71	  - reset-names: Must include the following entries:
72	    - isp
73	
74	- gr2d: 2D graphics engine
75	
76	  Required properties:
77	  - compatible: "nvidia,tegra<chip>-gr2d"
78	  - reg: Physical base address and length of the controller's registers.
79	  - interrupts: The interrupt outputs from the controller.
80	  - clocks: Must contain one entry, for the module clock.
81	    See ../clocks/clock-bindings.txt for details.
82	  - resets: Must contain an entry for each entry in reset-names.
83	    See ../reset/reset.txt for details.
84	  - reset-names: Must include the following entries:
85	    - 2d
86	
87	- gr3d: 3D graphics engine
88	
89	  Required properties:
90	  - compatible: "nvidia,tegra<chip>-gr3d"
91	  - reg: Physical base address and length of the controller's registers.
92	  - clocks: Must contain an entry for each entry in clock-names.
93	    See ../clocks/clock-bindings.txt for details.
94	  - clock-names: Must include the following entries:
95	    (This property may be omitted if the only clock in the list is "3d")
96	    - 3d
97	      This MUST be the first entry.
98	    - 3d2 (Only required on SoCs with two 3D clocks)
99	  - resets: Must contain an entry for each entry in reset-names.
100	    See ../reset/reset.txt for details.
101	  - reset-names: Must include the following entries:
102	    - 3d
103	    - 3d2 (Only required on SoCs with two 3D clocks)
104	
105	- dc: display controller
106	
107	  Required properties:
108	  - compatible: "nvidia,tegra<chip>-dc"
109	  - reg: Physical base address and length of the controller's registers.
110	  - interrupts: The interrupt outputs from the controller.
111	  - clocks: Must contain an entry for each entry in clock-names.
112	    See ../clocks/clock-bindings.txt for details.
113	  - clock-names: Must include the following entries:
114	    - dc
115	      This MUST be the first entry.
116	    - parent
117	  - resets: Must contain an entry for each entry in reset-names.
118	    See ../reset/reset.txt for details.
119	  - reset-names: Must include the following entries:
120	    - dc
121	  - nvidia,head: The number of the display controller head. This is used to
122	    setup the various types of output to receive video data from the given
123	    head.
124	
125	  Each display controller node has a child node, named "rgb", that represents
126	  the RGB output associated with the controller. It can take the following
127	  optional properties:
128	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
129	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
130	  - nvidia,edid: supplies a binary EDID blob
131	  - nvidia,panel: phandle of a display panel
132	
133	- hdmi: High Definition Multimedia Interface
134	
135	  Required properties:
136	  - compatible: "nvidia,tegra<chip>-hdmi"
137	  - reg: Physical base address and length of the controller's registers.
138	  - interrupts: The interrupt outputs from the controller.
139	  - vdd-supply: regulator for supply voltage
140	  - pll-supply: regulator for PLL
141	  - clocks: Must contain an entry for each entry in clock-names.
142	    See ../clocks/clock-bindings.txt for details.
143	  - clock-names: Must include the following entries:
144	    - hdmi
145	      This MUST be the first entry.
146	    - parent
147	  - resets: Must contain an entry for each entry in reset-names.
148	    See ../reset/reset.txt for details.
149	  - reset-names: Must include the following entries:
150	    - hdmi
151	
152	  Optional properties:
153	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
154	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
155	  - nvidia,edid: supplies a binary EDID blob
156	  - nvidia,panel: phandle of a display panel
157	
158	- tvo: TV encoder output
159	
160	  Required properties:
161	  - compatible: "nvidia,tegra<chip>-tvo"
162	  - reg: Physical base address and length of the controller's registers.
163	  - interrupts: The interrupt outputs from the controller.
164	  - clocks: Must contain one entry, for the module clock.
165	    See ../clocks/clock-bindings.txt for details.
166	
167	- dsi: display serial interface
168	
169	  Required properties:
170	  - compatible: "nvidia,tegra<chip>-dsi"
171	  - reg: Physical base address and length of the controller's registers.
172	  - clocks: Must contain an entry for each entry in clock-names.
173	    See ../clocks/clock-bindings.txt for details.
174	  - clock-names: Must include the following entries:
175	    - dsi
176	      This MUST be the first entry.
177	    - lp
178	    - parent
179	  - resets: Must contain an entry for each entry in reset-names.
180	    See ../reset/reset.txt for details.
181	  - reset-names: Must include the following entries:
182	    - dsi
183	  - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
184	    which pads are used by this DSI output and need to be calibrated. See also
185	    ../mipi/nvidia,tegra114-mipi.txt.
186	
187	  Optional properties:
188	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
189	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
190	  - nvidia,edid: supplies a binary EDID blob
191	  - nvidia,panel: phandle of a display panel
192	
193	- sor: serial output resource
194	
195	  Required properties:
196	  - compatible: "nvidia,tegra124-sor"
197	  - reg: Physical base address and length of the controller's registers.
198	  - interrupts: The interrupt outputs from the controller.
199	  - clocks: Must contain an entry for each entry in clock-names.
200	    See ../clocks/clock-bindings.txt for details.
201	  - clock-names: Must include the following entries:
202	    - sor: clock input for the SOR hardware
203	    - parent: input for the pixel clock
204	    - dp: reference clock for the SOR clock
205	    - safe: safe reference for the SOR clock during power up
206	  - resets: Must contain an entry for each entry in reset-names.
207	    See ../reset/reset.txt for details.
208	  - reset-names: Must include the following entries:
209	    - sor
210	
211	  Optional properties:
212	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
213	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
214	  - nvidia,edid: supplies a binary EDID blob
215	  - nvidia,panel: phandle of a display panel
216	
217	  Optional properties when driving an eDP output:
218	  - nvidia,dpaux: phandle to a DispayPort AUX interface
219	
220	- dpaux: DisplayPort AUX interface
221	  - compatible: "nvidia,tegra124-dpaux"
222	  - reg: Physical base address and length of the controller's registers.
223	  - interrupts: The interrupt outputs from the controller.
224	  - clocks: Must contain an entry for each entry in clock-names.
225	    See ../clocks/clock-bindings.txt for details.
226	  - clock-names: Must include the following entries:
227	    - dpaux: clock input for the DPAUX hardware
228	    - parent: reference clock
229	  - resets: Must contain an entry for each entry in reset-names.
230	    See ../reset/reset.txt for details.
231	  - reset-names: Must include the following entries:
232	    - dpaux
233	  - vdd-supply: phandle of a supply that powers the DisplayPort link
234	
235	Example:
236	
237	/ {
238		...
239	
240		host1x {
241			compatible = "nvidia,tegra20-host1x", "simple-bus";
242			reg = <0x50000000 0x00024000>;
243			interrupts = <0 65 0x04   /* mpcore syncpt */
244				      0 67 0x04>; /* mpcore general */
245			clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
246			resets = <&tegra_car 28>;
247			reset-names = "host1x";
248	
249			#address-cells = <1>;
250			#size-cells = <1>;
251	
252			ranges = <0x54000000 0x54000000 0x04000000>;
253	
254			mpe {
255				compatible = "nvidia,tegra20-mpe";
256				reg = <0x54040000 0x00040000>;
257				interrupts = <0 68 0x04>;
258				clocks = <&tegra_car TEGRA20_CLK_MPE>;
259				resets = <&tegra_car 60>;
260				reset-names = "mpe";
261			};
262	
263			vi {
264				compatible = "nvidia,tegra20-vi";
265				reg = <0x54080000 0x00040000>;
266				interrupts = <0 69 0x04>;
267				clocks = <&tegra_car TEGRA20_CLK_VI>;
268				resets = <&tegra_car 100>;
269				reset-names = "vi";
270			};
271	
272			epp {
273				compatible = "nvidia,tegra20-epp";
274				reg = <0x540c0000 0x00040000>;
275				interrupts = <0 70 0x04>;
276				clocks = <&tegra_car TEGRA20_CLK_EPP>;
277				resets = <&tegra_car 19>;
278				reset-names = "epp";
279			};
280	
281			isp {
282				compatible = "nvidia,tegra20-isp";
283				reg = <0x54100000 0x00040000>;
284				interrupts = <0 71 0x04>;
285				clocks = <&tegra_car TEGRA20_CLK_ISP>;
286				resets = <&tegra_car 23>;
287				reset-names = "isp";
288			};
289	
290			gr2d {
291				compatible = "nvidia,tegra20-gr2d";
292				reg = <0x54140000 0x00040000>;
293				interrupts = <0 72 0x04>;
294				clocks = <&tegra_car TEGRA20_CLK_GR2D>;
295				resets = <&tegra_car 21>;
296				reset-names = "2d";
297			};
298	
299			gr3d {
300				compatible = "nvidia,tegra20-gr3d";
301				reg = <0x54180000 0x00040000>;
302				clocks = <&tegra_car TEGRA20_CLK_GR3D>;
303				resets = <&tegra_car 24>;
304				reset-names = "3d";
305			};
306	
307			dc@54200000 {
308				compatible = "nvidia,tegra20-dc";
309				reg = <0x54200000 0x00040000>;
310				interrupts = <0 73 0x04>;
311				clocks = <&tegra_car TEGRA20_CLK_DISP1>,
312					 <&tegra_car TEGRA20_CLK_PLL_P>;
313				clock-names = "dc", "parent";
314				resets = <&tegra_car 27>;
315				reset-names = "dc";
316	
317				rgb {
318					status = "disabled";
319				};
320			};
321	
322			dc@54240000 {
323				compatible = "nvidia,tegra20-dc";
324				reg = <0x54240000 0x00040000>;
325				interrupts = <0 74 0x04>;
326				clocks = <&tegra_car TEGRA20_CLK_DISP2>,
327					 <&tegra_car TEGRA20_CLK_PLL_P>;
328				clock-names = "dc", "parent";
329				resets = <&tegra_car 26>;
330				reset-names = "dc";
331	
332				rgb {
333					status = "disabled";
334				};
335			};
336	
337			hdmi {
338				compatible = "nvidia,tegra20-hdmi";
339				reg = <0x54280000 0x00040000>;
340				interrupts = <0 75 0x04>;
341				clocks = <&tegra_car TEGRA20_CLK_HDMI>,
342					 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
343				clock-names = "hdmi", "parent";
344				resets = <&tegra_car 51>;
345				reset-names = "hdmi";
346				status = "disabled";
347			};
348	
349			tvo {
350				compatible = "nvidia,tegra20-tvo";
351				reg = <0x542c0000 0x00040000>;
352				interrupts = <0 76 0x04>;
353				clocks = <&tegra_car TEGRA20_CLK_TVO>;
354				status = "disabled";
355			};
356	
357			dsi {
358				compatible = "nvidia,tegra20-dsi";
359				reg = <0x54300000 0x00040000>;
360				clocks = <&tegra_car TEGRA20_CLK_DSI>,
361					 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
362				clock-names = "dsi", "parent";
363				resets = <&tegra_car 48>;
364				reset-names = "dsi";
365				status = "disabled";
366			};
367		};
368	
369		...
370	};
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