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Documentation / devicetree / bindings / gpu / nvidia,tegra20-host1x.txt




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Based on kernel version 4.3. Page generated on 2015-11-02 12:45 EST.

1	NVIDIA Tegra host1x
2	
3	Required properties:
4	- compatible: "nvidia,tegra<chip>-host1x"
5	- reg: Physical base address and length of the controller's registers.
6	- interrupts: The interrupt outputs from the controller.
7	- #address-cells: The number of cells used to represent physical base addresses
8	  in the host1x address space. Should be 1.
9	- #size-cells: The number of cells used to represent the size of an address
10	  range in the host1x address space. Should be 1.
11	- ranges: The mapping of the host1x address space to the CPU address space.
12	- clocks: Must contain one entry, for the module clock.
13	  See ../clocks/clock-bindings.txt for details.
14	- resets: Must contain an entry for each entry in reset-names.
15	  See ../reset/reset.txt for details.
16	- reset-names: Must include the following entries:
17	  - host1x
18	
19	The host1x top-level node defines a number of children, each representing one
20	of the following host1x client modules:
21	
22	- mpe: video encoder
23	
24	  Required properties:
25	  - compatible: "nvidia,tegra<chip>-mpe"
26	  - reg: Physical base address and length of the controller's registers.
27	  - interrupts: The interrupt outputs from the controller.
28	  - clocks: Must contain one entry, for the module clock.
29	    See ../clocks/clock-bindings.txt for details.
30	  - resets: Must contain an entry for each entry in reset-names.
31	    See ../reset/reset.txt for details.
32	  - reset-names: Must include the following entries:
33	    - mpe
34	
35	- vi: video input
36	
37	  Required properties:
38	  - compatible: "nvidia,tegra<chip>-vi"
39	  - reg: Physical base address and length of the controller's registers.
40	  - interrupts: The interrupt outputs from the controller.
41	  - clocks: Must contain one entry, for the module clock.
42	    See ../clocks/clock-bindings.txt for details.
43	  - resets: Must contain an entry for each entry in reset-names.
44	    See ../reset/reset.txt for details.
45	  - reset-names: Must include the following entries:
46	    - vi
47	
48	- epp: encoder pre-processor
49	
50	  Required properties:
51	  - compatible: "nvidia,tegra<chip>-epp"
52	  - reg: Physical base address and length of the controller's registers.
53	  - interrupts: The interrupt outputs from the controller.
54	  - clocks: Must contain one entry, for the module clock.
55	    See ../clocks/clock-bindings.txt for details.
56	  - resets: Must contain an entry for each entry in reset-names.
57	    See ../reset/reset.txt for details.
58	  - reset-names: Must include the following entries:
59	    - epp
60	
61	- isp: image signal processor
62	
63	  Required properties:
64	  - compatible: "nvidia,tegra<chip>-isp"
65	  - reg: Physical base address and length of the controller's registers.
66	  - interrupts: The interrupt outputs from the controller.
67	  - clocks: Must contain one entry, for the module clock.
68	    See ../clocks/clock-bindings.txt for details.
69	  - resets: Must contain an entry for each entry in reset-names.
70	    See ../reset/reset.txt for details.
71	  - reset-names: Must include the following entries:
72	    - isp
73	
74	- gr2d: 2D graphics engine
75	
76	  Required properties:
77	  - compatible: "nvidia,tegra<chip>-gr2d"
78	  - reg: Physical base address and length of the controller's registers.
79	  - interrupts: The interrupt outputs from the controller.
80	  - clocks: Must contain one entry, for the module clock.
81	    See ../clocks/clock-bindings.txt for details.
82	  - resets: Must contain an entry for each entry in reset-names.
83	    See ../reset/reset.txt for details.
84	  - reset-names: Must include the following entries:
85	    - 2d
86	
87	- gr3d: 3D graphics engine
88	
89	  Required properties:
90	  - compatible: "nvidia,tegra<chip>-gr3d"
91	  - reg: Physical base address and length of the controller's registers.
92	  - clocks: Must contain an entry for each entry in clock-names.
93	    See ../clocks/clock-bindings.txt for details.
94	  - clock-names: Must include the following entries:
95	    (This property may be omitted if the only clock in the list is "3d")
96	    - 3d
97	      This MUST be the first entry.
98	    - 3d2 (Only required on SoCs with two 3D clocks)
99	  - resets: Must contain an entry for each entry in reset-names.
100	    See ../reset/reset.txt for details.
101	  - reset-names: Must include the following entries:
102	    - 3d
103	    - 3d2 (Only required on SoCs with two 3D clocks)
104	
105	- dc: display controller
106	
107	  Required properties:
108	  - compatible: "nvidia,tegra<chip>-dc"
109	  - reg: Physical base address and length of the controller's registers.
110	  - interrupts: The interrupt outputs from the controller.
111	  - clocks: Must contain an entry for each entry in clock-names.
112	    See ../clocks/clock-bindings.txt for details.
113	  - clock-names: Must include the following entries:
114	    - dc
115	      This MUST be the first entry.
116	    - parent
117	  - resets: Must contain an entry for each entry in reset-names.
118	    See ../reset/reset.txt for details.
119	  - reset-names: Must include the following entries:
120	    - dc
121	  - nvidia,head: The number of the display controller head. This is used to
122	    setup the various types of output to receive video data from the given
123	    head.
124	
125	  Each display controller node has a child node, named "rgb", that represents
126	  the RGB output associated with the controller. It can take the following
127	  optional properties:
128	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
129	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
130	  - nvidia,edid: supplies a binary EDID blob
131	  - nvidia,panel: phandle of a display panel
132	
133	- hdmi: High Definition Multimedia Interface
134	
135	  Required properties:
136	  - compatible: "nvidia,tegra<chip>-hdmi"
137	  - reg: Physical base address and length of the controller's registers.
138	  - interrupts: The interrupt outputs from the controller.
139	  - hdmi-supply: supply for the +5V HDMI connector pin
140	  - vdd-supply: regulator for supply voltage
141	  - pll-supply: regulator for PLL
142	  - clocks: Must contain an entry for each entry in clock-names.
143	    See ../clocks/clock-bindings.txt for details.
144	  - clock-names: Must include the following entries:
145	    - hdmi
146	      This MUST be the first entry.
147	    - parent
148	  - resets: Must contain an entry for each entry in reset-names.
149	    See ../reset/reset.txt for details.
150	  - reset-names: Must include the following entries:
151	    - hdmi
152	
153	  Optional properties:
154	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
155	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
156	  - nvidia,edid: supplies a binary EDID blob
157	  - nvidia,panel: phandle of a display panel
158	
159	- tvo: TV encoder output
160	
161	  Required properties:
162	  - compatible: "nvidia,tegra<chip>-tvo"
163	  - reg: Physical base address and length of the controller's registers.
164	  - interrupts: The interrupt outputs from the controller.
165	  - clocks: Must contain one entry, for the module clock.
166	    See ../clocks/clock-bindings.txt for details.
167	
168	- dsi: display serial interface
169	
170	  Required properties:
171	  - compatible: "nvidia,tegra<chip>-dsi"
172	  - reg: Physical base address and length of the controller's registers.
173	  - clocks: Must contain an entry for each entry in clock-names.
174	    See ../clocks/clock-bindings.txt for details.
175	  - clock-names: Must include the following entries:
176	    - dsi
177	      This MUST be the first entry.
178	    - lp
179	    - parent
180	  - resets: Must contain an entry for each entry in reset-names.
181	    See ../reset/reset.txt for details.
182	  - reset-names: Must include the following entries:
183	    - dsi
184	  - avdd-dsi-supply: phandle of a supply that powers the DSI controller
185	  - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
186	    which pads are used by this DSI output and need to be calibrated. See also
187	    ../mipi/nvidia,tegra114-mipi.txt.
188	
189	  Optional properties:
190	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
191	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
192	  - nvidia,edid: supplies a binary EDID blob
193	  - nvidia,panel: phandle of a display panel
194	  - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
195	    up with in order to support up to 8 data lanes
196	
197	- sor: serial output resource
198	
199	  Required properties:
200	  - compatible: Should be:
201	    - "nvidia,tegra124-sor": for Tegra124 and Tegra132
202	    - "nvidia,tegra132-sor": for Tegra132
203	    - "nvidia,tegra210-sor": for Tegra210
204	    - "nvidia,tegra210-sor1": for Tegra210
205	  - reg: Physical base address and length of the controller's registers.
206	  - interrupts: The interrupt outputs from the controller.
207	  - clocks: Must contain an entry for each entry in clock-names.
208	    See ../clocks/clock-bindings.txt for details.
209	  - clock-names: Must include the following entries:
210	    - sor: clock input for the SOR hardware
211	    - parent: input for the pixel clock
212	    - dp: reference clock for the SOR clock
213	    - safe: safe reference for the SOR clock during power up
214	  - resets: Must contain an entry for each entry in reset-names.
215	    See ../reset/reset.txt for details.
216	  - reset-names: Must include the following entries:
217	    - sor
218	
219	  Optional properties:
220	  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
221	  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
222	  - nvidia,edid: supplies a binary EDID blob
223	  - nvidia,panel: phandle of a display panel
224	
225	  Optional properties when driving an eDP output:
226	  - nvidia,dpaux: phandle to a DispayPort AUX interface
227	
228	- dpaux: DisplayPort AUX interface
229	  - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux".  Otherwise,
230	    must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
231	    <chip> is tegra132.
232	  - reg: Physical base address and length of the controller's registers.
233	  - interrupts: The interrupt outputs from the controller.
234	  - clocks: Must contain an entry for each entry in clock-names.
235	    See ../clocks/clock-bindings.txt for details.
236	  - clock-names: Must include the following entries:
237	    - dpaux: clock input for the DPAUX hardware
238	    - parent: reference clock
239	  - resets: Must contain an entry for each entry in reset-names.
240	    See ../reset/reset.txt for details.
241	  - reset-names: Must include the following entries:
242	    - dpaux
243	  - vdd-supply: phandle of a supply that powers the DisplayPort link
244	
245	Example:
246	
247	/ {
248		...
249	
250		host1x {
251			compatible = "nvidia,tegra20-host1x", "simple-bus";
252			reg = <0x50000000 0x00024000>;
253			interrupts = <0 65 0x04   /* mpcore syncpt */
254				      0 67 0x04>; /* mpcore general */
255			clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
256			resets = <&tegra_car 28>;
257			reset-names = "host1x";
258	
259			#address-cells = <1>;
260			#size-cells = <1>;
261	
262			ranges = <0x54000000 0x54000000 0x04000000>;
263	
264			mpe {
265				compatible = "nvidia,tegra20-mpe";
266				reg = <0x54040000 0x00040000>;
267				interrupts = <0 68 0x04>;
268				clocks = <&tegra_car TEGRA20_CLK_MPE>;
269				resets = <&tegra_car 60>;
270				reset-names = "mpe";
271			};
272	
273			vi {
274				compatible = "nvidia,tegra20-vi";
275				reg = <0x54080000 0x00040000>;
276				interrupts = <0 69 0x04>;
277				clocks = <&tegra_car TEGRA20_CLK_VI>;
278				resets = <&tegra_car 100>;
279				reset-names = "vi";
280			};
281	
282			epp {
283				compatible = "nvidia,tegra20-epp";
284				reg = <0x540c0000 0x00040000>;
285				interrupts = <0 70 0x04>;
286				clocks = <&tegra_car TEGRA20_CLK_EPP>;
287				resets = <&tegra_car 19>;
288				reset-names = "epp";
289			};
290	
291			isp {
292				compatible = "nvidia,tegra20-isp";
293				reg = <0x54100000 0x00040000>;
294				interrupts = <0 71 0x04>;
295				clocks = <&tegra_car TEGRA20_CLK_ISP>;
296				resets = <&tegra_car 23>;
297				reset-names = "isp";
298			};
299	
300			gr2d {
301				compatible = "nvidia,tegra20-gr2d";
302				reg = <0x54140000 0x00040000>;
303				interrupts = <0 72 0x04>;
304				clocks = <&tegra_car TEGRA20_CLK_GR2D>;
305				resets = <&tegra_car 21>;
306				reset-names = "2d";
307			};
308	
309			gr3d {
310				compatible = "nvidia,tegra20-gr3d";
311				reg = <0x54180000 0x00040000>;
312				clocks = <&tegra_car TEGRA20_CLK_GR3D>;
313				resets = <&tegra_car 24>;
314				reset-names = "3d";
315			};
316	
317			dc@54200000 {
318				compatible = "nvidia,tegra20-dc";
319				reg = <0x54200000 0x00040000>;
320				interrupts = <0 73 0x04>;
321				clocks = <&tegra_car TEGRA20_CLK_DISP1>,
322					 <&tegra_car TEGRA20_CLK_PLL_P>;
323				clock-names = "dc", "parent";
324				resets = <&tegra_car 27>;
325				reset-names = "dc";
326	
327				rgb {
328					status = "disabled";
329				};
330			};
331	
332			dc@54240000 {
333				compatible = "nvidia,tegra20-dc";
334				reg = <0x54240000 0x00040000>;
335				interrupts = <0 74 0x04>;
336				clocks = <&tegra_car TEGRA20_CLK_DISP2>,
337					 <&tegra_car TEGRA20_CLK_PLL_P>;
338				clock-names = "dc", "parent";
339				resets = <&tegra_car 26>;
340				reset-names = "dc";
341	
342				rgb {
343					status = "disabled";
344				};
345			};
346	
347			hdmi {
348				compatible = "nvidia,tegra20-hdmi";
349				reg = <0x54280000 0x00040000>;
350				interrupts = <0 75 0x04>;
351				clocks = <&tegra_car TEGRA20_CLK_HDMI>,
352					 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
353				clock-names = "hdmi", "parent";
354				resets = <&tegra_car 51>;
355				reset-names = "hdmi";
356				status = "disabled";
357			};
358	
359			tvo {
360				compatible = "nvidia,tegra20-tvo";
361				reg = <0x542c0000 0x00040000>;
362				interrupts = <0 76 0x04>;
363				clocks = <&tegra_car TEGRA20_CLK_TVO>;
364				status = "disabled";
365			};
366	
367			dsi {
368				compatible = "nvidia,tegra20-dsi";
369				reg = <0x54300000 0x00040000>;
370				clocks = <&tegra_car TEGRA20_CLK_DSI>,
371					 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
372				clock-names = "dsi", "parent";
373				resets = <&tegra_car 48>;
374				reset-names = "dsi";
375				status = "disabled";
376			};
377		};
378	
379		...
380	};
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