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Documentation / devicetree / bindings / interrupt-controller / brcm,bcm2835-armctrl-ic.txt




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Based on kernel version 4.7.2. Page generated on 2016-08-22 22:42 EST.

1	BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
2	
3	The BCM2835 contains a custom top-level interrupt controller, which supports
4	72 interrupt sources using a 2-level register scheme. The interrupt
5	controller, or the HW block containing it, is referred to occasionally
6	as "armctrl" in the SoC documentation, hence naming of this binding.
7	
8	The BCM2836 contains the same interrupt controller with the same
9	interrupts, but the per-CPU interrupt controller is the root, and an
10	interrupt there indicates that the ARMCTRL has an interrupt to handle.
11	
12	Required properties:
13	
14	- compatible : should be "brcm,bcm2835-armctrl-ic" or
15	                 "brcm,bcm2836-armctrl-ic"
16	- reg : Specifies base physical address and size of the registers.
17	- interrupt-controller : Identifies the node as an interrupt controller
18	- #interrupt-cells : Specifies the number of cells needed to encode an
19	  interrupt source. The value shall be 2.
20	
21	  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
22	  pending" register, or 1/2 respectively for interrupts in the "IRQ pending
23	  1/2" register.
24	
25	  The 2nd cell contains the interrupt number within the bank. Valid values
26	  are 0..7 for bank 0, and 0..31 for bank 1.
27	
28	Additional required properties for brcm,bcm2836-armctrl-ic:
29	- interrupt-parent : Specifies the parent interrupt controller when this
30	  controller is the second level.
31	- interrupts : Specifies the interrupt on the parent for this interrupt
32	  controller to handle.
33	
34	The interrupt sources are as follows:
35	
36	Bank 0:
37	0: ARM_TIMER
38	1: ARM_MAILBOX
39	2: ARM_DOORBELL_0
40	3: ARM_DOORBELL_1
41	4: VPU0_HALTED
42	5: VPU1_HALTED
43	6: ILLEGAL_TYPE0
44	7: ILLEGAL_TYPE1
45	
46	Bank 1:
47	0: TIMER0
48	1: TIMER1
49	2: TIMER2
50	3: TIMER3
51	4: CODEC0
52	5: CODEC1
53	6: CODEC2
54	7: VC_JPEG
55	8: ISP
56	9: VC_USB
57	10: VC_3D
58	11: TRANSPOSER
59	12: MULTICORESYNC0
60	13: MULTICORESYNC1
61	14: MULTICORESYNC2
62	15: MULTICORESYNC3
63	16: DMA0
64	17: DMA1
65	18: VC_DMA2
66	19: VC_DMA3
67	20: DMA4
68	21: DMA5
69	22: DMA6
70	23: DMA7
71	24: DMA8
72	25: DMA9
73	26: DMA10
74	27: DMA11-14 - shared interrupt for DMA 11 to 14
75	28: DMAALL - triggers on all dma interrupts (including chanel 15)
76	29: AUX
77	30: ARM
78	31: VPUDMA
79	
80	Bank 2:
81	0: HOSTPORT
82	1: VIDEOSCALER
83	2: CCP2TX
84	3: SDC
85	4: DSI0
86	5: AVE
87	6: CAM0
88	7: CAM1
89	8: HDMI0
90	9: HDMI1
91	10: PIXELVALVE1
92	11: I2CSPISLV
93	12: DSI1
94	13: PWA0
95	14: PWA1
96	15: CPR
97	16: SMI
98	17: GPIO0
99	18: GPIO1
100	19: GPIO2
101	20: GPIO3
102	21: VC_I2C
103	22: VC_SPI
104	23: VC_I2SPCM
105	24: VC_SDIO
106	25: VC_UART
107	26: SLIMBUS
108	27: VEC
109	28: CPG
110	29: RNG
111	30: VC_ARASANSDIO
112	31: AVSPMON
113	
114	Example:
115	
116	/* BCM2835, first level */
117	intc: interrupt-controller {
118		compatible = "brcm,bcm2835-armctrl-ic";
119		reg = <0x7e00b200 0x200>;
120		interrupt-controller;
121		#interrupt-cells = <2>;
122	};
123	
124	/* BCM2836, second level */
125	intc: interrupt-controller {
126		compatible = "brcm,bcm2836-armctrl-ic";
127		reg = <0x7e00b200 0x200>;
128		interrupt-controller;
129		#interrupt-cells = <2>;
130	
131		interrupt-parent = <&local_intc>;
132		interrupts = <8>;
133	};
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