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Documentation / devicetree / bindings / mmc / sdhci-msm.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:37 EST.

1	* Qualcomm SDHCI controller (sdhci-msm)
2	
3	This file documents differences between the core properties in mmc.txt
4	and the properties used by the sdhci-msm driver.
5	
6	Required properties:
7	- compatible: Should contain "qcom,sdhci-msm-v4".
8	- reg: Base address and length of the register in the following order:
9		- Host controller register map (required)
10		- SD Core register map (required)
11	- interrupts: Should contain an interrupt-specifiers for the interrupts:
12		- Host controller interrupt (required)
13	- pinctrl-names: Should contain only one value - "default".
14	- pinctrl-0: Should specify pin control groups used for this controller.
15	- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
16	- clock-names: Should contain the following:
17		"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
18		"core"	- SDC MMC clock (MCLK) (required)
19		"bus"	- SDCC bus voter clock (optional)
20	
21	Example:
22	
23		sdhc_1: sdhci@f9824900 {
24			compatible = "qcom,sdhci-msm-v4";
25			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
26			interrupts = <0 123 0>;
27			bus-width = <8>;
28			non-removable;
29	
30			vmmc = <&pm8941_l20>;
31			vqmmc = <&pm8941_s3>;
32	
33			pinctrl-names = "default";
34			pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
35	
36			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
37			clock-names = "core", "iface";
38		};
39	
40		sdhc_2: sdhci@f98a4900 {
41			compatible = "qcom,sdhci-msm-v4";
42			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
43			interrupts = <0 125 0>;
44			bus-width = <4>;
45			cd-gpios = <&msmgpio 62 0x1>;
46	
47			vmmc = <&pm8941_l21>;
48			vqmmc = <&pm8941_l13>;
49	
50			pinctrl-names = "default";
51			pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
52	
53			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
54			clock-names = "core", "iface";
55		};
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