Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.
1 PXA3xx NAND DT bindings 2 3 Required properties: 4 5 - compatible: Should be set to one of the following: 6 marvell,pxa3xx-nand 7 marvell,armada370-nand 8 marvell,armada-8k-nand 9 - reg: The register base for the controller 10 - interrupts: The interrupt to map 11 - #address-cells: Set to <1> if the node includes partitions 12 - marvell,system-controller: Set to retrieve the syscon node that handles 13 NAND controller related registers (only required 14 with marvell,armada-8k-nand compatible). 15 16 Optional properties: 17 18 - dmas: dma data channel, see dma.txt binding doc 19 - marvell,nand-enable-arbiter: Set to enable the bus arbiter 20 - marvell,nand-keep-config: Set to keep the NAND controller config as set 21 by the bootloader 22 - num-cs: Number of chipselect lines to use 23 - nand-on-flash-bbt: boolean to enable on flash bbt option if 24 not present false 25 - nand-ecc-strength: number of bits to correct per ECC step 26 - nand-ecc-step-size: number of data bytes covered by a single ECC step 27 28 The following ECC strength and step size are currently supported: 29 30 - nand-ecc-strength = <1>, nand-ecc-step-size = <512> 31 - nand-ecc-strength = <4>, nand-ecc-step-size = <512> 32 - nand-ecc-strength = <8>, nand-ecc-step-size = <512> 33 34 Example: 35 36 nand0: nand@43100000 { 37 compatible = "marvell,pxa3xx-nand"; 38 reg = <0x43100000 90>; 39 interrupts = <45>; 40 dmas = <&pdma 97 0>; 41 dma-names = "data"; 42 #address-cells = <1>; 43 44 marvell,nand-enable-arbiter; 45 marvell,nand-keep-config; 46 num-cs = <1>; 47 48 /* partitions (optional) */ 49 };