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Documentation / devicetree / bindings / pci / nvidia,tegra20-pcie.txt




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Based on kernel version 4.1. Page generated on 2015-06-28 12:10 EST.

1	NVIDIA Tegra PCIe controller
2	
3	Required properties:
4	- compatible: For Tegra20, must contain "nvidia,tegra20-pcie".  For Tegra30,
5	  "nvidia,tegra30-pcie".  For Tegra124, must contain "nvidia,tegra124-pcie".
6	  Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
7	  <chip> is tegra132 or tegra210.
8	- device_type: Must be "pci"
9	- reg: A list of physical base address and length for each set of controller
10	  registers. Must contain an entry for each entry in the reg-names property.
11	- reg-names: Must include the following entries:
12	  "pads": PADS registers
13	  "afi": AFI registers
14	  "cs": configuration space region
15	- interrupts: A list of interrupt outputs of the controller. Must contain an
16	  entry for each entry in the interrupt-names property.
17	- interrupt-names: Must include the following entries:
18	  "intr": The Tegra interrupt that is asserted for controller interrupts
19	  "msi": The Tegra interrupt that is asserted when an MSI is received
20	- bus-range: Range of bus numbers associated with this controller
21	- #address-cells: Address representation for root ports (must be 3)
22	  - cell 0 specifies the bus and device numbers of the root port:
23	    [23:16]: bus number
24	    [15:11]: device number
25	  - cell 1 denotes the upper 32 address bits and should be 0
26	  - cell 2 contains the lower 32 address bits and is used to translate to the
27	    CPU address space
28	- #size-cells: Size representation for root ports (must be 2)
29	- ranges: Describes the translation of addresses for root ports and standard
30	  PCI regions. The entries must be 6 cells each, where the first three cells
31	  correspond to the address as described for the #address-cells property
32	  above, the fourth cell is the physical CPU address to translate to and the
33	  fifth and six cells are as described for the #size-cells property above.
34	  - The first two entries are expected to translate the addresses for the root
35	    port registers, which are referenced by the assigned-addresses property of
36	    the root port nodes (see below).
37	  - The remaining entries setup the mapping for the standard I/O, memory and
38	    prefetchable PCI regions. The first cell determines the type of region
39	    that is setup:
40	    - 0x81000000: I/O memory region
41	    - 0x82000000: non-prefetchable memory region
42	    - 0xc2000000: prefetchable memory region
43	  Please refer to the standard PCI bus binding document for a more detailed
44	  explanation.
45	- #interrupt-cells: Size representation for interrupts (must be 1)
46	- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
47	  Please refer to the standard PCI bus binding document for a more detailed
48	  explanation.
49	- clocks: Must contain an entry for each entry in clock-names.
50	  See ../clocks/clock-bindings.txt for details.
51	- clock-names: Must include the following entries:
52	  - pex
53	  - afi
54	  - pll_e
55	  - cml (not required for Tegra20)
56	- resets: Must contain an entry for each entry in reset-names.
57	  See ../reset/reset.txt for details.
58	- reset-names: Must include the following entries:
59	  - pex
60	  - afi
61	  - pcie_x
62	
63	Required properties on Tegra124 and later:
64	- phys: Must contain an entry for each entry in phy-names.
65	- phy-names: Must include the following entries:
66	  - pcie
67	
68	Power supplies for Tegra20:
69	- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
70	- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
71	- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
72	  supply 1.05 V.
73	- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
74	  supply 1.05 V.
75	- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
76	
77	Power supplies for Tegra30:
78	- Required:
79	  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
80	    supply 1.05 V.
81	  - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
82	    supply 1.05 V.
83	  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
84	    supply 1.8 V.
85	  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
86	    Must supply 3.3 V.
87	- Optional:
88	  - If lanes 0 to 3 are used:
89	    - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
90	    - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
91	  - If lanes 4 or 5 are used:
92	    - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
93	    - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
94	
95	Power supplies for Tegra124:
96	- Required:
97	  - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
98	  - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
99	  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
100	    supply 1.05 V.
101	  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
102	    Must supply 3.3 V.
103	  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
104	    Must supply 3.3 V.
105	  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
106	    supply 2.8-3.3 V.
107	  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
108	    supply 1.05 V.
109	
110	Root ports are defined as subnodes of the PCIe controller node.
111	
112	Required properties:
113	- device_type: Must be "pci"
114	- assigned-addresses: Address and size of the port configuration registers
115	- reg: PCI bus address of the root port
116	- #address-cells: Must be 3
117	- #size-cells: Must be 2
118	- ranges: Sub-ranges distributed from the PCIe controller node. An empty
119	  property is sufficient.
120	- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
121	  are:
122	  - Root port 0 uses 4 lanes, root port 1 is unused.
123	  - Both root ports use 2 lanes.
124	
125	Example:
126	
127	SoC DTSI:
128	
129		pcie-controller {
130			compatible = "nvidia,tegra20-pcie";
131			device_type = "pci";
132			reg = <0x80003000 0x00000800   /* PADS registers */
133			       0x80003800 0x00000200   /* AFI registers */
134			       0x90000000 0x10000000>; /* configuration space */
135			reg-names = "pads", "afi", "cs";
136			interrupts = <0 98 0x04   /* controller interrupt */
137			              0 99 0x04>; /* MSI interrupt */
138			interrupt-names = "intr", "msi";
139	
140			#interrupt-cells = <1>;
141			interrupt-map-mask = <0 0 0 0>;
142			interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
143	
144			bus-range = <0x00 0xff>;
145			#address-cells = <3>;
146			#size-cells = <2>;
147	
148			ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
149				  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
150				  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
151				  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
152				  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
153	
154			clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
155			clock-names = "pex", "afi", "pll_e";
156			resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
157			reset-names = "pex", "afi", "pcie_x";
158			status = "disabled";
159	
160			pci@1,0 {
161				device_type = "pci";
162				assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
163				reg = <0x000800 0 0 0 0>;
164				status = "disabled";
165	
166				#address-cells = <3>;
167				#size-cells = <2>;
168	
169				ranges;
170	
171				nvidia,num-lanes = <2>;
172			};
173	
174			pci@2,0 {
175				device_type = "pci";
176				assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
177				reg = <0x001000 0 0 0 0>;
178				status = "disabled";
179	
180				#address-cells = <3>;
181				#size-cells = <2>;
182	
183				ranges;
184	
185				nvidia,num-lanes = <2>;
186			};
187		};
188	
189	
190	Board DTS:
191	
192		pcie-controller {
193			status = "okay";
194	
195			vdd-supply = <&pci_vdd_reg>;
196			pex-clk-supply = <&pci_clk_reg>;
197	
198			/* root port 00:01.0 */
199			pci@1,0 {
200				status = "okay";
201	
202				/* bridge 01:00.0 (optional) */
203				pci@0,0 {
204					reg = <0x010000 0 0 0 0>;
205	
206					#address-cells = <3>;
207					#size-cells = <2>;
208	
209					device_type = "pci";
210	
211					/* endpoint 02:00.0 */
212					pci@0,0 {
213						reg = <0x020000 0 0 0 0>;
214					};
215				};
216			};
217		};
218	
219	Note that devices on the PCI bus are dynamically discovered using PCI's bus
220	enumeration and therefore don't need corresponding device nodes in DT. However
221	if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
222	device nodes need to be added in order to allow the bus' children to be
223	instantiated at the proper location in the operating system's device tree (as
224	illustrated by the optional nodes in the example above).
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