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Documentation / devicetree / bindings / pinctrl / allwinner,sunxi-pinctrl.txt




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Based on kernel version 4.3. Page generated on 2015-11-02 12:46 EST.

1	* Allwinner A1X Pin Controller
2	
3	The pins controlled by sunXi pin controller are organized in banks,
4	each bank has 32 pins.  Each pin has 7 multiplexing functions, with
5	the first two functions being GPIO in and out. The configuration on
6	the pins includes drive strength and pull-up.
7	
8	Required properties:
9	- compatible: Should be one of the followings (depending on you SoC):
10	  "allwinner,sun4i-a10-pinctrl"
11	  "allwinner,sun5i-a10s-pinctrl"
12	  "allwinner,sun5i-a13-pinctrl"
13	  "allwinner,sun6i-a31-pinctrl"
14	  "allwinner,sun6i-a31s-pinctrl"
15	  "allwinner,sun6i-a31-r-pinctrl"
16	  "allwinner,sun7i-a20-pinctrl"
17	  "allwinner,sun8i-a23-pinctrl"
18	  "allwinner,sun8i-a23-r-pinctrl"
19	  "allwinner,sun8i-a33-pinctrl"
20	
21	- reg: Should contain the register physical address and length for the
22	  pin controller.
23	
24	Please refer to pinctrl-bindings.txt in this directory for details of the
25	common pinctrl bindings used by client devices.
26	
27	A pinctrl node should contain at least one subnodes representing the
28	pinctrl groups available on the machine. Each subnode will list the
29	pins it needs, and how they should be configured, with regard to muxer
30	configuration, drive strength and pullups. If one of these options is
31	not set, its actual value will be unspecified.
32	
33	Required subnode-properties:
34	
35	- allwinner,pins: List of strings containing the pin name.
36	- allwinner,function: Function to mux the pins listed above to.
37	
38	Optional subnode-properties:
39	- allwinner,drive: Integer. Represents the current sent to the pin
40	    0: 10 mA
41	    1: 20 mA
42	    2: 30 mA
43	    3: 40 mA
44	- allwinner,pull: Integer.
45	    0: No resistor
46	    1: Pull-up resistor
47	    2: Pull-down resistor
48	
49	Examples:
50	
51	pio: pinctrl@01c20800 {
52		compatible = "allwinner,sun5i-a13-pinctrl";
53		reg = <0x01c20800 0x400>;
54		#address-cells = <1>;
55		#size-cells = <0>;
56	
57		uart1_pins_a: uart1@0 {
58			allwinner,pins = "PE10", "PE11";
59			allwinner,function = "uart1";
60			allwinner,drive = <0>;
61			allwinner,pull = <0>;
62		};
63	
64		uart1_pins_b: uart1@1 {
65			allwinner,pins = "PG3", "PG4";
66			allwinner,function = "uart1";
67			allwinner,drive = <0>;
68			allwinner,pull = <0>;
69		};
70	};
71	
72	
73	GPIO and interrupt controller
74	-----------------------------
75	
76	This hardware also acts as a GPIO controller and an interrupt
77	controller.
78	
79	Consumers that would want to refer to one or the other (or both)
80	should provide through the usual *-gpios and interrupts properties a
81	cell with 3 arguments, first the number of the bank, then the pin
82	inside that bank, and finally the flags for the GPIO/interrupts.
83	
84	Example:
85	
86	xio: gpio@38 {
87		compatible = "nxp,pcf8574a";
88		reg = <0x38>;
89	
90		gpio-controller;
91		#gpio-cells = <2>;
92	
93		interrupt-parent = <&pio>;
94		interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
95		interrupt-controller;
96		#interrupt-cells = <2>;
97	};
98	
99	reg_usb1_vbus: usb1-vbus {
100		compatible = "regulator-fixed";
101		regulator-name = "usb1-vbus";
102		regulator-min-microvolt = <5000000>;
103		regulator-max-microvolt = <5000000>;
104		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
105	};
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