Documentation / devicetree / bindings / powerpc / fsl / dma.txt


Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204
* Freescale DMA Controllers

** Freescale Elo DMA Controller
   This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
   series chips such as mpc8315, mpc8349, mpc8379 etc.

Required properties:

- compatible        : must include "fsl,elo-dma"
- reg               : DMA General Status Register, i.e. DGSR which contains
                      status for all the 4 DMA channels
- ranges            : describes the mapping between the address space of the
                      DMA channels and the address space of the DMA controller
- cell-index        : controller index.  0 for controller @ 0x8100
- interrupts        : interrupt specifier for DMA IRQ

- DMA channel nodes:
        - compatible        : must include "fsl,elo-dma-channel"
                              However, see note below.
        - reg               : DMA channel specific registers
        - cell-index        : DMA channel index starts at 0.

Optional properties:
        - interrupts        : interrupt specifier for DMA channel IRQ
                              (on 83xx this is expected to be identical to
                              the interrupts property of the parent node)

Example:
	dma@82a8 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
		reg = <0x82a8 4>;
		ranges = <0 0x8100 0x1a4>;
		interrupt-parent = <&ipic>;
		interrupts = <71 8>;
		cell-index = <0>;
		dma-channel@0 {
			compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
			cell-index = <0>;
			reg = <0 0x80>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
		};
		dma-channel@80 {
			compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
			cell-index = <1>;
			reg = <0x80 0x80>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
		};
		dma-channel@100 {
			compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
			cell-index = <2>;
			reg = <0x100 0x80>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
		};
		dma-channel@180 {
			compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
			cell-index = <3>;
			reg = <0x180 0x80>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
		};
	};

** Freescale EloPlus DMA Controller
   This is a 4-channel DMA controller with extended addresses and chaining,
   mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
   mpc8540, mpc8641 p4080, bsc9131 etc.

Required properties:

- compatible        : must include "fsl,eloplus-dma"
- reg               : DMA General Status Register, i.e. DGSR which contains
                      status for all the 4 DMA channels
- cell-index        : controller index.  0 for controller @ 0x21000,
                                         1 for controller @ 0xc000
- ranges            : describes the mapping between the address space of the
                      DMA channels and the address space of the DMA controller

- DMA channel nodes:
        - compatible        : must include "fsl,eloplus-dma-channel"
                              However, see note below.
        - cell-index        : DMA channel index starts at 0.
        - reg               : DMA channel specific registers
        - interrupts        : interrupt specifier for DMA channel IRQ

Example:
	dma@21300 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
		reg = <0x21300 4>;
		ranges = <0 0x21100 0x200>;
		cell-index = <0>;
		dma-channel@0 {
			compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
			reg = <0 0x80>;
			cell-index = <0>;
			interrupt-parent = <&mpic>;
			interrupts = <20 2>;
		};
		dma-channel@80 {
			compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
			reg = <0x80 0x80>;
			cell-index = <1>;
			interrupt-parent = <&mpic>;
			interrupts = <21 2>;
		};
		dma-channel@100 {
			compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
			reg = <0x100 0x80>;
			cell-index = <2>;
			interrupt-parent = <&mpic>;
			interrupts = <22 2>;
		};
		dma-channel@180 {
			compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
			reg = <0x180 0x80>;
			cell-index = <3>;
			interrupt-parent = <&mpic>;
			interrupts = <23 2>;
		};
	};

** Freescale Elo3 DMA Controller
   DMA controller which has same function as EloPlus except that Elo3 has 8
   channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
   series chips, such as t1040, t4240, b4860.

Required properties:

- compatible        : must include "fsl,elo3-dma"
- reg               : contains two entries for DMA General Status Registers,
                      i.e. DGSR0 which includes status for channel 1~4, and
                      DGSR1 for channel 5~8
- ranges            : describes the mapping between the address space of the
                      DMA channels and the address space of the DMA controller

- DMA channel nodes:
        - compatible        : must include "fsl,eloplus-dma-channel"
        - reg               : DMA channel specific registers
        - interrupts        : interrupt specifier for DMA channel IRQ

Example:
dma@100300 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,elo3-dma";
	reg = <0x100300 0x4>,
	      <0x100600 0x4>;
	ranges = <0x0 0x100100 0x500>;
	dma-channel@0 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x0 0x80>;
		interrupts = <28 2 0 0>;
	};
	dma-channel@80 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x80 0x80>;
		interrupts = <29 2 0 0>;
	};
	dma-channel@100 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x100 0x80>;
		interrupts = <30 2 0 0>;
	};
	dma-channel@180 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x180 0x80>;
		interrupts = <31 2 0 0>;
	};
	dma-channel@300 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x300 0x80>;
		interrupts = <76 2 0 0>;
	};
	dma-channel@380 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x380 0x80>;
		interrupts = <77 2 0 0>;
	};
	dma-channel@400 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x400 0x80>;
		interrupts = <78 2 0 0>;
	};
	dma-channel@480 {
		compatible = "fsl,eloplus-dma-channel";
		reg = <0x480 0x80>;
		interrupts = <79 2 0 0>;
	};
};

Note on DMA channel compatible properties: The compatible property must say
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
driver (fsldma).  Any DMA channel used by fsldma cannot be used by another
DMA driver, such as the SSI sound drivers for the MPC8610.  Therefore, any DMA
channel that should be used for another driver should not use
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel".  For the SSI drivers, for
example, the compatible property should be "fsl,ssi-dma-channel".  See ssi.txt
for more information.