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Documentation / devicetree / bindings / spi / sh-msiof.txt




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Based on kernel version 4.0. Page generated on 2015-04-14 21:22 EST.

1	Renesas MSIOF spi controller
2	
3	Required properties:
4	- compatible           : "renesas,msiof-<soctype>" for SoCs,
5				 "renesas,sh-msiof" for SuperH, or
6				 "renesas,sh-mobile-msiof" for SH Mobile series.
7				 Examples with soctypes are:
8				 "renesas,msiof-r8a7790" (R-Car H2)
9				 "renesas,msiof-r8a7791" (R-Car M2-W)
10				 "renesas,msiof-r8a7792" (R-Car V2H)
11				 "renesas,msiof-r8a7793" (R-Car M2-N)
12				 "renesas,msiof-r8a7794" (R-Car E2)
13	- reg                  : A list of offsets and lengths of the register sets for
14				 the device.
15				 If only one register set is present, it is to be used
16				 by both the CPU and the DMA engine.
17				 If two register sets are present, the first is to be
18				 used by the CPU, and the second is to be used by the
19				 DMA engine.
20	- interrupt-parent     : The phandle for the interrupt controller that
21				 services interrupts for this device
22	- interrupts           : Interrupt specifier
23	- #address-cells       : Must be <1>
24	- #size-cells          : Must be <0>
25	
26	Optional properties:
27	- clocks               : Must contain a reference to the functional clock.
28	- num-cs               : Total number of chip-selects (default is 1)
29	- dmas                 : Must contain a list of two references to DMA
30				 specifiers, one for transmission, and one for
31				 reception.
32	- dma-names            : Must contain a list of two DMA names, "tx" and "rx".
33	- renesas,dtdl         : delay sync signal (setup) in transmit mode.
34				 Must contain one of the following values:
35				 0   (no bit delay)
36				 50  (0.5-clock-cycle delay)
37				 100 (1-clock-cycle delay)
38				 150 (1.5-clock-cycle delay)
39				 200 (2-clock-cycle delay)
40	
41	- renesas,syncdl       : delay sync signal (hold) in transmit mode.
42				 Must contain one of the following values:
43				 0   (no bit delay)
44				 50  (0.5-clock-cycle delay)
45				 100 (1-clock-cycle delay)
46				 150 (1.5-clock-cycle delay)
47				 200 (2-clock-cycle delay)
48				 300 (3-clock-cycle delay)
49	
50	Optional properties, deprecated for soctype-specific bindings:
51	- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
52				 (default is 64)
53	- renesas,rx-fifo-size : Overrides the default rx fifo size given in words
54				 (default is 64, or 256 on R-Car Gen2)
55	
56	Pinctrl properties might be needed, too.  See
57	Documentation/devicetree/bindings/pinctrl/renesas,*.
58	
59	Example:
60	
61		msiof0: spi@e6e20000 {
62			compatible = "renesas,msiof-r8a7791";
63			reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
64			interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
65			clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
66			dmas = <&dmac0 0x51>, <&dmac0 0x52>;
67			dma-names = "tx", "rx";
68			#address-cells = <1>;
69			#size-cells = <0>;
70			status = "disabled";
71		};
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