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Documentation / devicetree / bindings / spi / sh-msiof.txt




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Based on kernel version 4.7.2. Page generated on 2016-08-22 22:44 EST.

1	Renesas MSIOF spi controller
2	
3	Required properties:
4	- compatible           : "renesas,msiof-<soctype>" for SoCs,
5				 "renesas,sh-msiof" for SuperH, or
6				 "renesas,sh-mobile-msiof" for SH Mobile series.
7				 Examples with soctypes are:
8				 "renesas,msiof-r8a7790" (R-Car H2)
9				 "renesas,msiof-r8a7791" (R-Car M2-W)
10				 "renesas,msiof-r8a7792" (R-Car V2H)
11				 "renesas,msiof-r8a7793" (R-Car M2-N)
12				 "renesas,msiof-r8a7794" (R-Car E2)
13				 "renesas,msiof-sh73a0" (SH-Mobile AG5)
14	- reg                  : A list of offsets and lengths of the register sets for
15				 the device.
16				 If only one register set is present, it is to be used
17				 by both the CPU and the DMA engine.
18				 If two register sets are present, the first is to be
19				 used by the CPU, and the second is to be used by the
20				 DMA engine.
21	- interrupt-parent     : The phandle for the interrupt controller that
22				 services interrupts for this device
23	- interrupts           : Interrupt specifier
24	- #address-cells       : Must be <1>
25	- #size-cells          : Must be <0>
26	
27	Optional properties:
28	- clocks               : Must contain a reference to the functional clock.
29	- num-cs               : Total number of chip-selects (default is 1)
30	- dmas                 : Must contain a list of two references to DMA
31				 specifiers, one for transmission, and one for
32				 reception.
33	- dma-names            : Must contain a list of two DMA names, "tx" and "rx".
34	- renesas,dtdl         : delay sync signal (setup) in transmit mode.
35				 Must contain one of the following values:
36				 0   (no bit delay)
37				 50  (0.5-clock-cycle delay)
38				 100 (1-clock-cycle delay)
39				 150 (1.5-clock-cycle delay)
40				 200 (2-clock-cycle delay)
41	
42	- renesas,syncdl       : delay sync signal (hold) in transmit mode.
43				 Must contain one of the following values:
44				 0   (no bit delay)
45				 50  (0.5-clock-cycle delay)
46				 100 (1-clock-cycle delay)
47				 150 (1.5-clock-cycle delay)
48				 200 (2-clock-cycle delay)
49				 300 (3-clock-cycle delay)
50	
51	Optional properties, deprecated for soctype-specific bindings:
52	- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
53				 (default is 64)
54	- renesas,rx-fifo-size : Overrides the default rx fifo size given in words
55				 (default is 64)
56	
57	Pinctrl properties might be needed, too.  See
58	Documentation/devicetree/bindings/pinctrl/renesas,*.
59	
60	Example:
61	
62		msiof0: spi@e6e20000 {
63			compatible = "renesas,msiof-r8a7791";
64			reg = <0 0xe6e20000 0 0x0064>;
65			interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
66			clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
67			dmas = <&dmac0 0x51>, <&dmac0 0x52>;
68			dma-names = "tx", "rx";
69			#address-cells = <1>;
70			#size-cells = <0>;
71			status = "disabled";
72		};
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