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Documentation / devicetree / bindings / spi / spi-fsl-dspi.txt




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Based on kernel version 4.1. Page generated on 2015-06-28 12:11 EST.

1	ARM Freescale DSPI controller
2	
3	Required properties:
4	- compatible : "fsl,vf610-dspi"
5	- reg : Offset and length of the register set for the device
6	- interrupts : Should contain SPI controller interrupt
7	- clocks: from common clock binding: handle to dspi clock.
8	- clock-names: from common clock binding: Shall be "dspi".
9	- pinctrl-0: pin control group to be used for this controller.
10	- pinctrl-names: must contain a "default" entry.
11	- spi-num-chipselects : the number of the chipselect signals.
12	- bus-num : the slave chip chipselect signal number.
13	
14	Optional property:
15	- big-endian: If present the dspi device's registers are implemented
16	  in big endian mode, otherwise in native mode(same with CPU), for more
17	  detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
18	
19	Optional SPI slave node properties:
20	- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
21	  select and the start of clock signal, at the start of a transfer.
22	- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
23	  signal and deactivating chip select, at the end of a transfer.
24	
25	Example:
26	
27	dspi0@4002c000 {
28		#address-cells = <1>;
29		#size-cells = <0>;
30		compatible = "fsl,vf610-dspi";
31		reg = <0x4002c000 0x1000>;
32		interrupts = <0 67 0x04>;
33		clocks = <&clks VF610_CLK_DSPI0>;
34		clock-names = "dspi";
35		spi-num-chipselects = <5>;
36		bus-num = <0>;
37		pinctrl-names = "default";
38		pinctrl-0 = <&pinctrl_dspi0_1>;
39		big-endian;
40		status = "okay";
41	
42		sflash: at26df081a@0 {
43			#address-cells = <1>;
44			#size-cells = <1>;
45			compatible = "atmel,at26df081a";
46			spi-max-frequency = <16000000>;
47			spi-cpol;
48			spi-cpha;
49			reg = <0>;
50			linux,modalias = "m25p80";
51			modal = "at26df081a";
52			fsl,spi-cs-sck-delay = <100>;
53			fsl,spi-sck-cs-delay = <50>;
54		};
55	};
56	
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