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Documentation / devicetree / bindings / video / exynos_dp.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:02 EST.

1	The Exynos display port interface should be configured based on
2	the type of panel connected to it.
3	
4	We use two nodes:
5		-dp-controller node
6		-dptx-phy node(defined inside dp-controller node)
7	
8	For the DP-PHY initialization, we use the dptx-phy node.
9	Required properties for dptx-phy: deprecated, use phys and phy-names
10		-reg: deprecated
11			Base address of DP PHY register.
12		-samsung,enable-mask: deprecated
13			The bit-mask used to enable/disable DP PHY.
14	
15	For the Panel initialization, we read data from dp-controller node.
16	Required properties for dp-controller:
17		-compatible:
18			should be "samsung,exynos5-dp".
19		-reg:
20			physical base address of the controller and length
21			of memory mapped region.
22		-interrupts:
23			interrupt combiner values.
24		-clocks:
25			from common clock binding: handle to dp clock.
26		-clock-names:
27			from common clock binding: Shall be "dp".
28		-interrupt-parent:
29			phandle to Interrupt combiner node.
30		-phys:
31			from general PHY binding: the phandle for the PHY device.
32		-phy-names:
33			from general PHY binding: Should be "dp".
34		-samsung,color-space:
35			input video data format.
36				COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
37		-samsung,dynamic-range:
38			dynamic range for input video data.
39				VESA = 0, CEA = 1
40		-samsung,ycbcr-coeff:
41			YCbCr co-efficients for input video.
42				COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
43		-samsung,color-depth:
44			number of bits per colour component.
45				COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
46		-samsung,link-rate:
47			link rate supported by the panel.
48				LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
49		-samsung,lane-count:
50			number of lanes supported by the panel.
51				LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
52	
53	Optional properties for dp-controller:
54		-interlaced:
55			interlace scan mode.
56				Progressive if defined, Interlaced if not defined
57		-vsync-active-high:
58			VSYNC polarity configuration.
59				High if defined, Low if not defined
60		-hsync-active-high:
61			HSYNC polarity configuration.
62				High if defined, Low if not defined
63	
64	Example:
65	
66	SOC specific portion:
67		dp-controller {
68			compatible = "samsung,exynos5-dp";
69			reg = <0x145b0000 0x10000>;
70			interrupts = <10 3>;
71			interrupt-parent = <&combiner>;
72			clocks = <&clock 342>;
73			clock-names = "dp";
74	
75			phys = <&dp_phy>;
76			phy-names = "dp";
77		};
78	
79	Board Specific portion:
80		dp-controller {
81			samsung,color-space = <0>;
82			samsung,dynamic-range = <0>;
83			samsung,ycbcr-coeff = <0>;
84			samsung,color-depth = <1>;
85			samsung,link-rate = <0x0a>;
86			samsung,lane-count = <4>;
87		};
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