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Documentation / devicetree / bindings / video / exynos_dp.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:02 EST.

1	The Exynos display port interface should be configured based on
2	the type of panel connected to it.
3	
4	We use two nodes:
5		-dp-controller node
6		-dptx-phy node(defined inside dp-controller node)
7	
8	For the DP-PHY initialization, we use the dptx-phy node.
9	Required properties for dptx-phy: deprecated, use phys and phy-names
10		-reg: deprecated
11			Base address of DP PHY register.
12		-samsung,enable-mask: deprecated
13			The bit-mask used to enable/disable DP PHY.
14	
15	For the Panel initialization, we read data from dp-controller node.
16	Required properties for dp-controller:
17		-compatible:
18			should be "samsung,exynos5-dp".
19		-reg:
20			physical base address of the controller and length
21			of memory mapped region.
22		-interrupts:
23			interrupt combiner values.
24		-clocks:
25			from common clock binding: handle to dp clock.
26		-clock-names:
27			from common clock binding: Shall be "dp".
28		-interrupt-parent:
29			phandle to Interrupt combiner node.
30		-phys:
31			from general PHY binding: the phandle for the PHY device.
32		-phy-names:
33			from general PHY binding: Should be "dp".
34		-samsung,color-space:
35			input video data format.
36				COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
37		-samsung,dynamic-range:
38			dynamic range for input video data.
39				VESA = 0, CEA = 1
40		-samsung,ycbcr-coeff:
41			YCbCr co-efficients for input video.
42				COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
43		-samsung,color-depth:
44			number of bits per colour component.
45				COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
46		-samsung,link-rate:
47			link rate supported by the panel.
48				LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
49		-samsung,lane-count:
50			number of lanes supported by the panel.
51				LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
52		- display-timings: timings for the connected panel as described by
53			Documentation/devicetree/bindings/video/display-timing.txt
54	
55	Optional properties for dp-controller:
56		-interlaced:
57			interlace scan mode.
58				Progressive if defined, Interlaced if not defined
59		-vsync-active-high:
60			VSYNC polarity configuration.
61				High if defined, Low if not defined
62		-hsync-active-high:
63			HSYNC polarity configuration.
64				High if defined, Low if not defined
65	
66	Example:
67	
68	SOC specific portion:
69		dp-controller {
70			compatible = "samsung,exynos5-dp";
71			reg = <0x145b0000 0x10000>;
72			interrupts = <10 3>;
73			interrupt-parent = <&combiner>;
74			clocks = <&clock 342>;
75			clock-names = "dp";
76	
77			phys = <&dp_phy>;
78			phy-names = "dp";
79		};
80	
81	Board Specific portion:
82		dp-controller {
83			samsung,color-space = <0>;
84			samsung,dynamic-range = <0>;
85			samsung,ycbcr-coeff = <0>;
86			samsung,color-depth = <1>;
87			samsung,link-rate = <0x0a>;
88			samsung,lane-count = <4>;
89	
90			display-timings {
91				native-mode = <&lcd_timing>;
92				lcd_timing: 1366x768 {
93					clock-frequency = <70589280>;
94					hactive = <1366>;
95					vactive = <768>;
96					hfront-porch = <40>;
97					hback-porch = <40>;
98					hsync-len = <32>;
99					vback-porch = <10>;
100					vfront-porch = <12>;
101					vsync-len = <6>;
102				};
103			};
104		};
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