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Documentation / devicetree / bindings / video / exynos_dp.txt




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Based on kernel version 3.9. Page generated on 2013-05-02 23:02 EST.

1	The Exynos display port interface should be configured based on
2	the type of panel connected to it.
3	
4	We use two nodes:
5		-dp-controller node
6		-dptx-phy node(defined inside dp-controller node)
7	
8	For the DP-PHY initialization, we use the dptx-phy node.
9	Required properties for dptx-phy:
10		-reg:
11			Base address of DP PHY register.
12		-samsung,enable-mask:
13			The bit-mask used to enable/disable DP PHY.
14	
15	For the Panel initialization, we read data from dp-controller node.
16	Required properties for dp-controller:
17		-compatible:
18			should be "samsung,exynos5-dp".
19		-reg:
20			physical base address of the controller and length
21			of memory mapped region.
22		-interrupts:
23			interrupt combiner values.
24		-interrupt-parent:
25			phandle to Interrupt combiner node.
26		-samsung,color-space:
27			input video data format.
28				COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
29		-samsung,dynamic-range:
30			dynamic range for input video data.
31				VESA = 0, CEA = 1
32		-samsung,ycbcr-coeff:
33			YCbCr co-efficients for input video.
34				COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
35		-samsung,color-depth:
36			number of bits per colour component.
37				COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
38		-samsung,link-rate:
39			link rate supported by the panel.
40				LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
41		-samsung,lane-count:
42			number of lanes supported by the panel.
43				LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
44	
45	Optional properties for dp-controller:
46		-interlaced:
47			interlace scan mode.
48				Progressive if defined, Interlaced if not defined
49		-vsync-active-high:
50			VSYNC polarity configuration.
51				High if defined, Low if not defined
52		-hsync-active-high:
53			HSYNC polarity configuration.
54				High if defined, Low if not defined
55	
56	Example:
57	
58	SOC specific portion:
59		dp-controller {
60			compatible = "samsung,exynos5-dp";
61			reg = <0x145b0000 0x10000>;
62			interrupts = <10 3>;
63			interrupt-parent = <&combiner>;
64	
65			dptx-phy {
66				reg = <0x10040720>;
67				samsung,enable-mask = <1>;
68			};
69	
70		};
71	
72	Board Specific portion:
73		dp-controller {
74			samsung,color-space = <0>;
75			samsung,dynamic-range = <0>;
76			samsung,ycbcr-coeff = <0>;
77			samsung,color-depth = <1>;
78			samsung,link-rate = <0x0a>;
79			samsung,lane-count = <4>;
80		};
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