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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:05 EST.

1	
2	Below is what the bt878 data book says about the PCI bug compatibility
3	modes of the bt878 chip.
4	
5	The triton1 insmod option sets the EN_TBFX bit in the control register.
6	The vsfx insmod option does the same for EN_VSFX bit.  If you have
7	stability problems you can try if one of these options makes your box
8	work solid.
9	
10	drivers/pci/quirks.c knows about these issues, this way these bits are
11	enabled automagically for known-buggy chipsets (look at the kernel
12	messages, bttv tells you).
13	
14	HTH,
15	
16	  Gerd
17	
18	---------------------------- cut here --------------------------
19	
20	Normal PCI Mode
21	---------------
22	
23	The PCI REQ signal is the logical-or of the incoming function requests.
24	The inter-nal GNT[0:1] signals are gated asynchronously with GNT and
25	demultiplexed by the audio request signal. Thus the arbiter defaults to
26	the video function at power-up and parks there during no requests for
27	bus access. This is desirable since the video will request the bus more
28	often. However, the audio will have highest bus access priority. Thus
29	the audio will have first access to the bus even when issuing a request
30	after the video request but before the PCI external arbiter has granted
31	access to the Bt879. Neither function can preempt the other once on the
32	bus. The duration to empty the entire video PCI FIFO onto the PCI bus is
33	very short compared to the bus access latency the audio PCI FIFO can
34	tolerate.
35	
36	
37	430FX Compatibility Mode
38	------------------------
39	
40	When using the 430FX PCI, the following rules will ensure
41	compatibility:
42	
43	 (1) Deassert REQ at the same time as asserting FRAME.
44	 (2) Do not reassert REQ to request another bus transaction until after
45	     finish-ing the previous transaction.
46	
47	Since the individual bus masters do not have direct control of REQ, a
48	simple logical-or of video and audio requests would violate the rules.
49	Thus, both the arbiter and the initiator contain 430FX compatibility
50	mode logic. To enable 430FX mode, set the EN_TBFX bit as indicated in
51	Device Control Register on page 104.
52	
53	When EN_TBFX is enabled, the arbiter ensures that the two compatibility
54	rules are satisfied. Before GNT is asserted by the PCI arbiter, this
55	internal arbiter may still logical-or the two requests. However, once
56	the GNT is issued, this arbiter must lock in its decision and now route
57	only the granted request to the REQ pin. The arbiter decision lock
58	happens regardless of the state of FRAME because it does not know when
59	FRAME will be asserted (typically - each initiator will assert FRAME on
60	the cycle following GNT). When FRAME is asserted, it is the initiator s
61	responsibility to remove its request at the same time. It is the
62	arbiters responsibility to allow this request to flow through to REQ and
63	not allow the other request to hold REQ asserted. The decision lock may
64	be removed at the end of the transaction: for example, when the bus is
65	idle (FRAME and IRDY). The arbiter decision may then continue
66	asynchronously until GNT is again asserted.
67	
68	
69	Interfacing with Non-PCI 2.1 Compliant Core Logic
70	-------------------------------------------------
71	
72	A small percentage of core logic devices may start a bus transaction
73	during the same cycle that GNT is de-asserted. This is non PCI 2.1
74	compliant. To ensure compatibility when using PCs with these PCI
75	controllers, the EN_VSFX bit must be enabled (refer to Device Control
76	Register on page 104). When in this mode, the arbiter does not pass GNT
77	to the internal functions unless REQ is asserted. This prevents a bus
78	transaction from starting the same cycle as GNT is de-asserted. This
79	also has the side effect of not being able to take advantage of bus
80	parking, thus lowering arbitration performance. The Bt879 drivers must
81	query for these non-compliant devices, and set the EN_VSFX bit only if
82	required.
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