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Documentation / virtual / kvm / devices / mpic.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:05 EST.

1	MPIC interrupt controller
2	=========================
3	
4	Device types supported:
5	  KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0
6	  KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2
7	
8	Only one MPIC instance, of any type, may be instantiated.  The created
9	MPIC will act as the system interrupt controller, connecting to each
10	vcpu's interrupt inputs.
11	
12	Groups:
13	  KVM_DEV_MPIC_GRP_MISC
14	  Attributes:
15	    KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
16	      Base address of the 256 KiB MPIC register space.  Must be
17	      naturally aligned.  A value of zero disables the mapping.
18	      Reset value is zero.
19	
20	  KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
21	    Access an MPIC register, as if the access were made from the guest.
22	    "attr" is the byte offset into the MPIC register space.  Accesses
23	    must be 4-byte aligned.
24	
25	    MSIs may be signaled by using this attribute group to write
26	    to the relevant MSIIR.
27	
28	  KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
29	    IRQ input line for each standard openpic source.  0 is inactive and 1
30	    is active, regardless of interrupt sense.
31	
32	    For edge-triggered interrupts:  Writing 1 is considered an activating
33	    edge, and writing 0 is ignored.  Reading returns 1 if a previously
34	    signaled edge has not been acknowledged, and 0 otherwise.
35	
36	    "attr" is the IRQ number.  IRQ numbers for standard sources are the
37	    byte offset of the relevant IVPR from EIVPR0, divided by 32.
38	
39	IRQ Routing:
40	
41	  The MPIC emulation supports IRQ routing. Only a single MPIC device can
42	  be instantiated. Once that device has been created, it's available as
43	  irqchip id 0.
44	
45	  This irqchip 0 has 256 interrupt pins, which expose the interrupts in
46	  the main array of interrupt sources (a.k.a. "SRC" interrupts).
47	
48	  The numbering is the same as the MPIC device tree binding -- based on
49	  the register offset from the beginning of the sources array, without
50	  regard to any subdivisions in chip documentation such as "internal"
51	  or "external" interrupts.
52	
53	  Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.
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