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Documentation / xtensa / atomctl.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:41 EST.

1	We Have Atomic Operation Control (ATOMCTL) Register.
2	This register determines the effect of using a S32C1I instruction
3	with various combinations of:
4	
5	     1. With and without an Coherent Cache Controller which
6	        can do Atomic Transactions to the memory internally.
7	
8	     2. With and without An Intelligent Memory Controller which
9	        can do Atomic Transactions itself.
10	
11	The Core comes up with a default value of for the three types of cache ops:
12	
13	      0x28: (WB: Internal, WT: Internal, BY:Exception)
14	
15	On the FPGA Cards we typically simulate an Intelligent Memory controller
16	which can implement  RCW transactions. For FPGA cards with an External
17	Memory controller we let it to the atomic operations internally while
18	doing a Cached (WB) transaction and use the Memory RCW for un-cached
19	operations.
20	
21	For systems without an coherent cache controller, non-MX, we always
22	use the memory controllers RCW, thought non-MX controlers likely
23	support the Internal Operation.
24	
25	CUSTOMER-WARNING:
26	   Virtually all customers buy their memory controllers from vendors that
27	   don't support atomic RCW memory transactions and will likely want to
28	   configure this register to not use RCW.
29	
30	Developers might find using RCW in Bypass mode convenient when testing
31	with the cache being bypassed; for example studying cache alias problems.
32	
33	See Section 4.3.12.4 of ISA; Bits:
34	
35	                             WB     WT      BY
36	                           5   4 | 3   2 | 1   0
37	  2 Bit
38	  Field
39	  Values     WB - Write Back         WT - Write Thru         BY - Bypass
40	---------    ---------------         -----------------     ----------------
41	    0        Exception               Exception               Exception
42	    1        RCW Transaction         RCW Transaction         RCW Transaction
43	    2        Internal Operation      Internal Operation      Reserved
44	    3        Reserved                Reserved                Reserved
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