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Documentation / devicetree / bindings / arm / arch_timer.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:54 EST.

1	* ARM architected timer
2	
3	ARM cores may have a per-core architected timer, which provides per-cpu timers,
4	or a memory mapped architected timer, which provides up to 8 frames with a
5	physical and optional virtual timer per frame.
6	
7	The per-core architected timer is attached to a GIC to deliver its
8	per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
9	to deliver its interrupts via SPIs.
10	
11	** CP15 Timer node properties:
12	
13	- compatible : Should at least contain one of
14		"arm,armv7-timer"
15		"arm,armv8-timer"
16	
17	- interrupts : Interrupt list for secure, non-secure, virtual and
18	  hypervisor timers, in that order.
19	
20	- clock-frequency : The frequency of the main counter, in Hz. Should be present
21	  only where necessary to work around broken firmware which does not configure
22	  CNTFRQ on all CPUs to a uniform correct value. Use of this property is
23	  strongly discouraged; fix your firmware unless absolutely impossible.
24	
25	- always-on : a boolean property. If present, the timer is powered through an
26	  always-on power domain, therefore it never loses context.
27	
28	- fsl,erratum-a008585 : A boolean property. Indicates the presence of
29	  QorIQ erratum A-008585, which says that reading the counter is
30	  unreliable unless the same value is returned by back-to-back reads.
31	  This also affects writes to the tval register, due to the implicit
32	  counter read.
33	
34	- hisilicon,erratum-161010101 : A boolean property. Indicates the
35	  presence of Hisilicon erratum 161010101, which says that reading the
36	  counters is unreliable in some cases, and reads may return a value 32
37	  beyond the correct value. This also affects writes to the tval
38	  registers, due to the implicit counter read.
39	
40	** Optional properties:
41	
42	- arm,cpu-registers-not-fw-configured : Firmware does not initialize
43	  any of the generic timer CPU registers, which contain their
44	  architecturally-defined reset values. Only supported for 32-bit
45	  systems which follow the ARMv7 architected reset values.
46	
47	- arm,no-tick-in-suspend : The main counter does not tick when the system is in
48	  low-power system suspend on some SoCs. This behavior does not match the
49	  Architecture Reference Manual's specification that the system counter "must
50	  be implemented in an always-on power domain."
51	
52	
53	Example:
54	
55		timer {
56			compatible = "arm,cortex-a15-timer",
57				     "arm,armv7-timer";
58			interrupts = <1 13 0xf08>,
59				     <1 14 0xf08>,
60				     <1 11 0xf08>,
61				     <1 10 0xf08>;
62			clock-frequency = <100000000>;
63		};
64	
65	** Memory mapped timer node properties:
66	
67	- compatible : Should at least contain "arm,armv7-timer-mem".
68	
69	- clock-frequency : The frequency of the main counter, in Hz. Should be present
70	  only when firmware has not configured the MMIO CNTFRQ registers.
71	
72	- reg : The control frame base address.
73	
74	Note that #address-cells, #size-cells, and ranges shall be present to ensure
75	the CPU can address a frame's registers.
76	
77	A timer node has up to 8 frame sub-nodes, each with the following properties:
78	
79	- frame-number: 0 to 7.
80	
81	- interrupts : Interrupt list for physical and virtual timers in that order.
82	  The virtual timer interrupt is optional.
83	
84	- reg : The first and second view base addresses in that order. The second view
85	  base address is optional.
86	
87	- status : "disabled" indicates the frame is not available for use. Optional.
88	
89	Example:
90	
91		timer@f0000000 {
92			compatible = "arm,armv7-timer-mem";
93			#address-cells = <1>;
94			#size-cells = <1>;
95			ranges;
96			reg = <0xf0000000 0x1000>;
97			clock-frequency = <50000000>;
98	
99			frame@f0001000 {
100				frame-number = <0>
101				interrupts = <0 13 0x8>,
102					     <0 14 0x8>;
103				reg = <0xf0001000 0x1000>,
104				      <0xf0002000 0x1000>;
105			};
106	
107			frame@f0003000 {
108				frame-number = <1>
109				interrupts = <0 15 0x8>;
110				reg = <0xf0003000 0x1000>;
111				status = "disabled";
112			};
113		};
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