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Documentation / devicetree / bindings / arm / arch_timer.txt




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Based on kernel version 4.9. Page generated on 2016-12-21 14:28 EST.

1	* ARM architected timer
2	
3	ARM cores may have a per-core architected timer, which provides per-cpu timers,
4	or a memory mapped architected timer, which provides up to 8 frames with a
5	physical and optional virtual timer per frame.
6	
7	The per-core architected timer is attached to a GIC to deliver its
8	per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
9	to deliver its interrupts via SPIs.
10	
11	** CP15 Timer node properties:
12	
13	- compatible : Should at least contain one of
14		"arm,armv7-timer"
15		"arm,armv8-timer"
16	
17	- interrupts : Interrupt list for secure, non-secure, virtual and
18	  hypervisor timers, in that order.
19	
20	- clock-frequency : The frequency of the main counter, in Hz. Should be present
21	  only where necessary to work around broken firmware which does not configure
22	  CNTFRQ on all CPUs to a uniform correct value. Use of this property is
23	  strongly discouraged; fix your firmware unless absolutely impossible.
24	
25	- always-on : a boolean property. If present, the timer is powered through an
26	  always-on power domain, therefore it never loses context.
27	
28	- fsl,erratum-a008585 : A boolean property. Indicates the presence of
29	  QorIQ erratum A-008585, which says that reading the counter is
30	  unreliable unless the same value is returned by back-to-back reads.
31	  This also affects writes to the tval register, due to the implicit
32	  counter read.
33	
34	** Optional properties:
35	
36	- arm,cpu-registers-not-fw-configured : Firmware does not initialize
37	  any of the generic timer CPU registers, which contain their
38	  architecturally-defined reset values. Only supported for 32-bit
39	  systems which follow the ARMv7 architected reset values.
40	
41	
42	Example:
43	
44		timer {
45			compatible = "arm,cortex-a15-timer",
46				     "arm,armv7-timer";
47			interrupts = <1 13 0xf08>,
48				     <1 14 0xf08>,
49				     <1 11 0xf08>,
50				     <1 10 0xf08>;
51			clock-frequency = <100000000>;
52		};
53	
54	** Memory mapped timer node properties:
55	
56	- compatible : Should at least contain "arm,armv7-timer-mem".
57	
58	- clock-frequency : The frequency of the main counter, in Hz. Should be present
59	  only when firmware has not configured the MMIO CNTFRQ registers.
60	
61	- reg : The control frame base address.
62	
63	Note that #address-cells, #size-cells, and ranges shall be present to ensure
64	the CPU can address a frame's registers.
65	
66	A timer node has up to 8 frame sub-nodes, each with the following properties:
67	
68	- frame-number: 0 to 7.
69	
70	- interrupts : Interrupt list for physical and virtual timers in that order.
71	  The virtual timer interrupt is optional.
72	
73	- reg : The first and second view base addresses in that order. The second view
74	  base address is optional.
75	
76	- status : "disabled" indicates the frame is not available for use. Optional.
77	
78	Example:
79	
80		timer@f0000000 {
81			compatible = "arm,armv7-timer-mem";
82			#address-cells = <1>;
83			#size-cells = <1>;
84			ranges;
85			reg = <0xf0000000 0x1000>;
86			clock-frequency = <50000000>;
87	
88			frame@f0001000 {
89				frame-number = <0>
90				interrupts = <0 13 0x8>,
91					     <0 14 0x8>;
92				reg = <0xf0001000 0x1000>,
93				      <0xf0002000 0x1000>;
94			};
95	
96			frame@f0003000 {
97				frame-number = <1>
98				interrupts = <0 15 0x8>;
99				reg = <0xf0003000 0x1000>;
100				status = "disabled";
101			};
102		};
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