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Documentation / devicetree / bindings / arm / exynos / power_domain.txt


Based on kernel version 4.3. Page generated on 2015-11-02 12:44 EST.

1	* Samsung Exynos Power Domains
2	
3	Exynos processors include support for multiple power domains which are used
4	to gate power to one or more peripherals on the processor.
5	
6	Required Properties:
7	- compatible: should be one of the following.
8	    * samsung,exynos4210-pd - for exynos4210 type power domain.
9	- reg: physical base address of the controller and length of memory mapped
10	    region.
11	- #power-domain-cells: number of cells in power domain specifier;
12	    must be 0.
13	
14	Optional Properties:
15	- clocks: List of clock handles. The parent clocks of the input clocks to the
16		devices in this power domain are set to oscclk before power gating
17		and restored back after powering on a domain. This is required for
18		all domains which are powered on and off and not required for unused
19		domains.
20	- clock-names: The following clocks can be specified:
21		- oscclk: Oscillator clock.
22		- clkN: Input clocks to the devices in this power domain. These clocks
23			will be reparented to oscclk before swithing power domain off.
24			Their original parent will be brought back after turning on
25			the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
26		- asbN: Clocks required by asynchronous bridges (ASB) present in
27			the power domain. These clock should be enabled during power
28			domain on/off operations.
29	- power-domains: phandle pointing to the parent power domain, for more details
30			 see Documentation/devicetree/bindings/power/power_domain.txt
31	
32	Node of a device using power domains must have a power-domains property
33	defined with a phandle to respective power domain.
34	
35	Example:
36	
37		lcd0: power-domain-lcd0 {
38			compatible = "samsung,exynos4210-pd";
39			reg = <0x10023C00 0x10>;
40			#power-domain-cells = <0>;
41		};
42	
43		mfc_pd: power-domain@10044060 {
44			compatible = "samsung,exynos4210-pd";
45			reg = <0x10044060 0x20>;
46			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
47				<&clock CLK_MOUT_USER_ACLK333>;
48			clock-names = "oscclk", "pclk0", "clk0";
49			#power-domain-cells = <0>;
50		};
51	
52	See Documentation/devicetree/bindings/power/power_domain.txt for description
53	of consumer-side bindings.
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