Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.
1 * ARM L2 Cache Controller 2 3 ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ 4 PL310 and variants) based level 2 cache controller. All these various implementations 5 of the L2 cache controller have compatible programming models (Note 1). 6 Some of the properties that are just prefixed "cache-*" are taken from section 7 3.7.3 of the Devicetree Specification which can be found at: 8 https://www.devicetree.org/specifications/ 9 10 The ARM L2 cache representation in the device tree should be done as follows: 11 12 Required properties: 13 14 - compatible : should be one of: 15 "arm,pl310-cache" 16 "arm,l220-cache" 17 "arm,l210-cache" 18 "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" 19 "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an 20 offset needs to be added to the address before passing down to the L2 21 cache controller 22 "marvell,aurora-system-cache": Marvell Controller designed to be 23 compatible with the ARM one, with system cache mode (meaning 24 maintenance operations on L1 are broadcasted to the L2 and L2 25 performs the same operation). 26 "marvell,aurora-outer-cache": Marvell Controller designed to be 27 compatible with the ARM one with outer cache mode. 28 "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible 29 with arm,pl310-cache controller. 30 - cache-unified : Specifies the cache is a unified cache. 31 - cache-level : Should be set to 2 for a level 2 cache. 32 - reg : Physical base address and size of cache controller's memory mapped 33 registers. 34 35 Optional properties: 36 37 - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of 38 read, write and setup latencies. Minimum valid values are 1. Controllers 39 without setup latency control should use a value of 0. 40 - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of 41 read, write and setup latencies. Controllers without setup latency control 42 should use 0. Controllers without separate read and write Tag RAM latency 43 values should only use the first cell. 44 - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. 45 - arm,filter-ranges : <start length> Starting address and length of window to 46 filter. Addresses in the filter window are directed to the M1 port. Other 47 addresses will go to the M0 port. 48 - arm,io-coherent : indicates that the system is operating in an hardware 49 I/O coherent mode. Valid only when the arm,pl310-cache compatible 50 string is used. 51 - interrupts : 1 combined interrupt. 52 - cache-size : specifies the size in bytes of the cache 53 - cache-sets : specifies the number of associativity sets of the cache 54 - cache-block-size : specifies the size in bytes of a cache block 55 - cache-line-size : specifies the size in bytes of a line in the cache, 56 if this is not specified, the line size is assumed to be equal to the 57 cache block size 58 - cache-id-part: cache id part number to be used if it is not present 59 on hardware 60 - wt-override: If present then L2 is forced to Write through mode 61 - arm,double-linefill : Override double linefill enable setting. Enable if 62 non-zero, disable if zero. 63 - arm,double-linefill-incr : Override double linefill on INCR read. Enable 64 if non-zero, disable if zero. 65 - arm,double-linefill-wrap : Override double linefill on WRAP read. Enable 66 if non-zero, disable if zero. 67 - arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero, 68 disable if zero. 69 - arm,prefetch-offset : Override prefetch offset value. Valid values are 70 0-7, 15, 23, and 31. 71 - arm,shared-override : The default behavior of the L220 or PL310 cache 72 controllers with respect to the shareable attribute is to transform "normal 73 memory non-cacheable transactions" into "cacheable no allocate" (for reads) 74 or "write through no write allocate" (for writes). 75 On systems where this may cause DMA buffer corruption, this property must be 76 specified to indicate that such transforms are precluded. 77 - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). 78 - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). 79 - arm,outer-sync-disable : disable the outer sync operation on the L2 cache. 80 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that 81 will randomly hang unless outer sync operations are disabled. 82 - prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> 83 (forcibly enable), property absent (retain settings set by firmware) 84 - prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), 85 <1> (forcibly enable), property absent (retain settings set by 86 firmware) 87 - arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly 88 disable), <1> (forcibly enable), property absent (OS specific behavior, 89 preferably retain firmware settings) 90 - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), 91 <1> (forcibly enable), property absent (OS specific behavior, 92 preferably retain firmware settings) 93 - arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) 94 - arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero 95 write (PL310) 96 97 Example: 98 99 L2: cache-controller { 100 compatible = "arm,pl310-cache"; 101 reg = <0xfff12000 0x1000>; 102 arm,data-latency = <1 1 1>; 103 arm,tag-latency = <2 2 2>; 104 arm,filter-ranges = <0x80000000 0x8000000>; 105 cache-unified; 106 cache-level = <2>; 107 interrupts = <45>; 108 }; 109 110 Note 1: The description in this document doesn't apply to integrated L2 111 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 112 integrated L2 controllers are assumed to be all preconfigured by 113 early secure boot code. Thus no need to deal with their configuration 114 in the kernel at all.