Based on kernel version 6.8
. Page generated on 2024-03-11 21:26 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 | OMAP PRCM bindings Power Reset and Clock Manager lists the device clocks and clockdomains under a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it, each describing one module and the clock hierarchy under it. see [1] for documentation about the individual clock/clockdomain nodes. [1] Documentation/devicetree/bindings/clock/ti/* Required properties: - compatible: Must be one of: "ti,am3-prcm" "ti,am4-prcm" "ti,omap2-prcm" "ti,omap3-prm" "ti,omap3-cm" "ti,omap4-cm1" "ti,omap4-prm" "ti,omap4-cm2" "ti,omap4-scrm" "ti,omap5-prm" "ti,omap5-cm-core-aon" "ti,omap5-scrm" "ti,omap5-cm-core" "ti,dra7-prm" "ti,dra7-cm-core-aon" "ti,dra7-cm-core" "ti,dm814-prcm" "ti,dm816-prcm" - reg: Contains PRCM module register address range (base address and length) - clocks: clocks for this module - clockdomains: clockdomains for this module - #clock-cells: From common clock binding - clock-output-names: From common clock binding Example: cm: clock@48004000 { compatible = "ti,omap3-cm"; reg = <0x48004000 0x4000>; #clock-cells = <0>; clock-output-names = "cm"; cm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_clockdomains: clockdomains { }; } &cm_clocks { omap2_32k_fck: omap_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; }; &cm_clockdomains { core_l3_clkdm: core_l3_clkdm { compatible = "ti,clockdomain"; clocks = <&sdrc_ick>; }; }; |