Based on kernel version 5.16
. Page generated on 2022-01-10 18:31 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 | * Samsung Exynos5410 Clock Controller The Exynos5410 clock controller generates and supplies clock to various controllers within the Exynos5410 SoC. Required Properties: - compatible: should be "samsung,exynos5410-clock" - reg: physical base address of the controller and length of memory mapped region. - #clock-cells: should be 1. - clocks: should contain an entry specifying the root clock from external oscillator supplied through XXTI or XusbXTI pin. This clock should be defined using standard clock bindings with "fin_pll" clock-output-name. That clock is being passed internally to the 9 PLLs. All available clocks are defined as preprocessor macros in dt-bindings/clock/exynos5410.h header and can be used in device tree sources. Example 1: An example of a clock controller node is listed below. fin_pll: xxti { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "fin_pll"; #clock-cells = <0>; }; clock: clock-controller@10010000 { compatible = "samsung,exynos5410-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; clocks = <&fin_pll>; }; Example 2: UART controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. serial@12c20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; interrupts = <0 51 0>; clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; }; |