Based on kernel version 5.7.10
. Page generated on 2020-07-23 22:17 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 | * Clock bindings for Freescale i.MX31 Required properties: - compatible: Should be "fsl,imx31-ccm" - reg: Address and length of the register set - interrupts: Should contain CCM interrupt - #clock-cells: Should be <1> The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. The following is a full list of i.MX31 clocks and IDs. Clock ID ----------------------- dummy 0 ckih 1 ckil 2 mpll 3 spll 4 upll 5 mcu_main 6 hsp 7 ahb 8 nfc 9 ipg 10 per_div 11 per 12 csi_sel 13 fir_sel 14 csi_div 15 usb_div_pre 16 usb_div_post 17 fir_div_pre 18 fir_div_post 19 sdhc1_gate 20 sdhc2_gate 21 gpt_gate 22 epit1_gate 23 epit2_gate 24 iim_gate 25 ata_gate 26 sdma_gate 27 cspi3_gate 28 rng_gate 29 uart1_gate 30 uart2_gate 31 ssi1_gate 32 i2c1_gate 33 i2c2_gate 34 i2c3_gate 35 hantro_gate 36 mstick1_gate 37 mstick2_gate 38 csi_gate 39 rtc_gate 40 wdog_gate 41 pwm_gate 42 sim_gate 43 ect_gate 44 usb_gate 45 kpp_gate 46 ipu_gate 47 uart3_gate 48 uart4_gate 49 uart5_gate 50 owire_gate 51 ssi2_gate 52 cspi1_gate 53 cspi2_gate 54 gacc_gate 55 emi_gate 56 rtic_gate 57 firi_gate 58 Examples: clks: ccm@53f80000{ compatible = "fsl,imx31-ccm"; reg = <0x53f80000 0x4000>; interrupts = <31>, <53>; #clock-cells = <1>; }; uart1: serial@43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; interrupts = <45>; clocks = <&clks 10>, <&clks 30>; clock-names = "ipg", "per"; }; |