Based on kernel version 6.8
. Page generated on 2024-03-11 21:26 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 | Binding for a Clockgen hardware block found on certain STMicroelectronics consumer electronics SoC devices. A Clockgen node can contain pll, diviser or multiplexer nodes. We will find only the base address of the Clockgen, this base address is common of all subnode. clockgen_node { reg = <>; pll_node { ... }; quadfs_node { ... }; mux_node { ... }; flexgen_node { ... }; ... }; This binding uses the common clock binding[1]. Each subnode should use the binding described in [2]..[7] [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt Required properties: - reg : A Base address and length of the register set. Example: clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; }; clk_s_a0_flexgen: clk-s-a0-flexgen { compatible = "st,flexgen"; #clock-cells = <1>; clocks = <&clk_s_a0_pll 0>, <&clk_sysin>; clock-output-names = "clk-ic-lmi0"; }; }; |