Based on kernel version 5.6.13
. Page generated on 2020-05-15 16:46 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 | UniPhier clock controller System clock ------------ Required properties: - compatible: should be one of the following: "socionext,uniphier-ld4-clock" - for LD4 SoC. "socionext,uniphier-pro4-clock" - for Pro4 SoC. "socionext,uniphier-sld8-clock" - for sLD8 SoC. "socionext,uniphier-pro5-clock" - for Pro5 SoC. "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC. "socionext,uniphier-ld11-clock" - for LD11 SoC. "socionext,uniphier-ld20-clock" - for LD20 SoC. "socionext,uniphier-pxs3-clock" - for PXs3 SoC - #clock-cells: should be 1. Example: sysctrl@61840000 { compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x4000>; clock { compatible = "socionext,uniphier-ld11-clock"; #clock-cells = <1>; }; other nodes ... }; Provided clocks: 8: ST DMAC 12: GIO (Giga bit stream I/O) 14: USB3 ch0 host 15: USB3 ch1 host 16: USB3 ch0 PHY0 17: USB3 ch0 PHY1 20: USB3 ch1 PHY0 21: USB3 ch1 PHY1 Media I/O (MIO) clock, SD clock ------------------------------- Required properties: - compatible: should be one of the following: "socionext,uniphier-ld4-mio-clock" - for LD4 SoC. "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC. "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC. "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC. "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC. "socionext,uniphier-ld11-mio-clock" - for LD11 SoC. "socionext,uniphier-ld20-sd-clock" - for LD20 SoC. "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC - #clock-cells: should be 1. Example: mioctrl@59810000 { compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; clock { compatible = "socionext,uniphier-ld11-mio-clock"; #clock-cells = <1>; }; other nodes ... }; Provided clocks: 0: SD ch0 host 1: eMMC host 2: SD ch1 host 7: MIO DMAC 8: USB2 ch0 host 9: USB2 ch1 host 10: USB2 ch2 host 12: USB2 ch0 PHY 13: USB2 ch1 PHY 14: USB2 ch2 PHY Peripheral clock ---------------- Required properties: - compatible: should be one of the following: "socionext,uniphier-ld4-peri-clock" - for LD4 SoC. "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC. "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC. "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC. "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC. "socionext,uniphier-ld11-peri-clock" - for LD11 SoC. "socionext,uniphier-ld20-peri-clock" - for LD20 SoC. "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC - #clock-cells: should be 1. Example: perictrl@59820000 { compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; clock { compatible = "socionext,uniphier-ld11-peri-clock"; #clock-cells = <1>; }; other nodes ... }; Provided clocks: 0: UART ch0 1: UART ch1 2: UART ch2 3: UART ch3 4: I2C ch0 5: I2C ch1 6: I2C ch2 7: I2C ch3 8: I2C ch4 9: I2C ch5 10: I2C ch6 |