Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.
1 * STMicroelectronics STM32 DMA controller 2 3 The STM32 DMA is a general-purpose direct memory access controller capable of 4 supporting 8 independent DMA channels. Each channel can have up to 8 requests. 5 6 Required properties: 7 - compatible: Should be "st,stm32-dma" 8 - reg: Should contain DMA registers location and length. This should include 9 all of the per-channel registers. 10 - interrupts: Should contain all of the per-channel DMA interrupts in 11 ascending order with respect to the DMA channel index. 12 - clocks: Should contain the input clock of the DMA instance. 13 - #dma-cells : Must be <4>. See DMA client paragraph for more details. 14 15 Optional properties: 16 - dma-requests : Number of DMA requests supported. 17 - resets: Reference to a reset controller asserting the DMA controller 18 - st,mem2mem: boolean; if defined, it indicates that the controller supports 19 memory-to-memory transfer 20 21 Example: 22 23 dma2: dma-controller@40026400 { 24 compatible = "st,stm32-dma"; 25 reg = <0x40026400 0x400>; 26 interrupts = <56>, 27 <57>, 28 <58>, 29 <59>, 30 <60>, 31 <68>, 32 <69>, 33 <70>; 34 clocks = <&clk_hclk>; 35 #dma-cells = <4>; 36 st,mem2mem; 37 resets = <&rcc 150>; 38 dma-requests = <8>; 39 }; 40 41 * DMA client 42 43 DMA clients connected to the STM32 DMA controller must use the format 44 described in the dma.txt file, using a four-cell specifier for each 45 channel: a phandle to the DMA controller plus the following four integer cells: 46 47 1. The channel id 48 2. The request line number 49 3. A 32bit mask specifying the DMA channel configuration which are device 50 dependent: 51 -bit 9: Peripheral Increment Address 52 0x0: no address increment between transfers 53 0x1: increment address between transfers 54 -bit 10: Memory Increment Address 55 0x0: no address increment between transfers 56 0x1: increment address between transfers 57 -bit 15: Peripheral Increment Offset Size 58 0x0: offset size is linked to the peripheral bus width 59 0x1: offset size is fixed to 4 (32-bit alignment) 60 -bit 16-17: Priority level 61 0x0: low 62 0x1: medium 63 0x2: high 64 0x3: very high 65 4. A 32bit mask specifying the DMA FIFO threshold configuration which are device 66 dependent: 67 -bit 0-1: Fifo threshold 68 0x0: 1/4 full FIFO 69 0x1: 1/2 full FIFO 70 0x2: 3/4 full FIFO 71 0x3: full FIFO 72 73 Example: 74 75 usart1: serial@40011000 { 76 compatible = "st,stm32-uart"; 77 reg = <0x40011000 0x400>; 78 interrupts = <37>; 79 clocks = <&clk_pclk2>; 80 dmas = <&dma2 2 4 0x10400 0x3>, 81 <&dma2 7 5 0x10200 0x3>; 82 dma-names = "rx", "tx"; 83 };