Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.
1 Allwinner A31 DMA Controller 2 3 This driver follows the generic DMA bindings defined in dma.txt. 4 5 Required properties: 6 7 - compatible: Must be one of 8 "allwinner,sun6i-a31-dma" 9 "allwinner,sun8i-a23-dma" 10 "allwinner,sun8i-a83t-dma" 11 "allwinner,sun8i-h3-dma" 12 "allwinner,sun8i-v3s-dma" 13 - reg: Should contain the registers base address and length 14 - interrupts: Should contain a reference to the interrupt used by this device 15 - clocks: Should contain a reference to the parent AHB clock 16 - resets: Should contain a reference to the reset controller asserting 17 this device in reset 18 - #dma-cells : Should be 1, a single cell holding a line request number 19 20 Example: 21 dma: dma-controller@1c02000 { 22 compatible = "allwinner,sun6i-a31-dma"; 23 reg = <0x01c02000 0x1000>; 24 interrupts = <0 50 4>; 25 clocks = <&ahb1_gates 6>; 26 resets = <&ahb1_rst 6>; 27 #dma-cells = <1>; 28 }; 29 30 ------------------------------------------------------------------------------ 31 For A64 DMA controller: 32 33 Required properties: 34 - compatible: "allwinner,sun50i-a64-dma" 35 - dma-channels: Number of DMA channels supported by the controller. 36 Refer to Documentation/devicetree/bindings/dma/dma.txt 37 - all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells 38 39 Optional properties: 40 - dma-requests: Number of DMA request signals supported by the controller. 41 Refer to Documentation/devicetree/bindings/dma/dma.txt 42 43 Example: 44 dma: dma-controller@1c02000 { 45 compatible = "allwinner,sun50i-a64-dma"; 46 reg = <0x01c02000 0x1000>; 47 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 48 clocks = <&ccu CLK_BUS_DMA>; 49 dma-channels = <8>; 50 dma-requests = <27>; 51 resets = <&ccu RST_BUS_DMA>; 52 #dma-cells = <1>; 53 }; 54 ------------------------------------------------------------------------------ 55 56 Clients: 57 58 DMA clients connected to the A31 DMA controller must use the format 59 described in the dma.txt file, using a two-cell specifier for each 60 channel: a phandle plus one integer cells. 61 The two cells in order are: 62 63 1. A phandle pointing to the DMA controller. 64 2. The port ID as specified in the datasheet 65 66 Example: 67 spi2: spi@1c6a000 { 68 compatible = "allwinner,sun6i-a31-spi"; 69 reg = <0x01c6a000 0x1000>; 70 interrupts = <0 67 4>; 71 clocks = <&ahb1_gates 22>, <&spi2_clk>; 72 clock-names = "ahb", "mod"; 73 dmas = <&dma 25>, <&dma 25>; 74 dma-names = "rx", "tx"; 75 resets = <&ahb1_rst 22>; 76 };