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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	Specifying GPIO information for devices
2	============================================
3	
4	1) gpios property
5	-----------------
6	
7	Nodes that makes use of GPIOs should specify them using one or more
8	properties, each containing a 'gpio-list':
9	
10		gpio-list ::= <single-gpio> [gpio-list]
11		single-gpio ::= <gpio-phandle> <gpio-specifier>
12		gpio-phandle : phandle to gpio controller node
13		gpio-specifier : Array of #gpio-cells specifying specific gpio
14				 (controller specific)
15	
16	GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17	of this GPIO for the device. While a non-existent <name> is considered valid
18	for compatibility reasons (resolving to the "gpios" property), it is not allowed
19	for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
20	bindings use it, but are only supported for compatibility reasons and should not
21	be used for newer bindings since it has been deprecated.
22	
23	GPIO properties can contain one or more GPIO phandles, but only in exceptional
24	cases should they contain more than one. If your device uses several GPIOs with
25	distinct functions, reference each of them under its own property, giving it a
26	meaningful name. The only case where an array of GPIOs is accepted is when
27	several GPIOs serve the same function (e.g. a parallel data line).
28	
29	The exact purpose of each gpios property must be documented in the device tree
30	binding of the device.
31	
32	The following example could be used to describe GPIO pins used as device enable
33	and bit-banged data signals:
34	
35		gpio1: gpio1 {
36			gpio-controller
37			 #gpio-cells = <2>;
38		};
39		gpio2: gpio2 {
40			gpio-controller
41			 #gpio-cells = <1>;
42		};
43		[...]
44	
45		enable-gpios = <&gpio2 2>;
46		data-gpios = <&gpio1 12 0>,
47			     <&gpio1 13 0>,
48			     <&gpio1 14 0>,
49			     <&gpio1 15 0>;
50	
51	Note that gpio-specifier length is controller dependent.  In the
52	above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
53	only uses one.
54	
55	gpio-specifier may encode: bank, pin position inside the bank,
56	whether pin is open-drain and whether pin is logically inverted.
57	
58	Exact meaning of each specifier cell is controller specific, and must
59	be documented in the device tree binding for the device.
60	
61	Most controllers are however specifying a generic flag bitfield
62	in the last cell, so for these, use the macros defined in
63	include/dt-bindings/gpio/gpio.h whenever possible:
64	
65	Example of a node using GPIOs:
66	
67		node {
68			enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
69		};
70	
71	GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
72	GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
73	
74	Optional standard bitfield specifiers for the last cell:
75	
76	- Bit 0: 0 means active high, 1 means active low
77	- Bit 1: 0 mean push-pull wiring, see:
78	           https://en.wikipedia.org/wiki/Push-pull_output
79	         1 means single-ended wiring, see:
80	           https://en.wikipedia.org/wiki/Single-ended_triode
81	- Bit 2: 0 means open-source, 1 means open drain, see:
82	           https://en.wikipedia.org/wiki/Open_collector
83	- Bit 3: 0 means the output should be maintained during sleep/low-power mode
84	         1 means the output state can be lost during sleep/low-power mode
85	
86	1.1) GPIO specifier best practices
87	----------------------------------
88	
89	A gpio-specifier should contain a flag indicating the GPIO polarity; active-
90	high or active-low. If it does, the following best practices should be
91	followed:
92	
93	The gpio-specifier's polarity flag should represent the physical level at the
94	GPIO controller that achieves (or represents, for inputs) a logically asserted
95	value at the device. The exact definition of logically asserted should be
96	defined by the binding for the device. If the board inverts the signal between
97	the GPIO controller and the device, then the gpio-specifier will represent the
98	opposite physical level than the signal at the device's pin.
99	
100	When the device's signal polarity is configurable, the binding for the
101	device must either:
102	
103	a) Define a single static polarity for the signal, with the expectation that
104	any software using that binding would statically program the device to use
105	that signal polarity.
106	
107	The static choice of polarity may be either:
108	
109	a1) (Preferred) Dictated by a binding-specific DT property.
110	
111	or:
112	
113	a2) Defined statically by the DT binding itself.
114	
115	In particular, the polarity cannot be derived from the gpio-specifier, since
116	that would prevent the DT from separately representing the two orthogonal
117	concepts of configurable signal polarity in the device, and possible board-
118	level signal inversion.
119	
120	or:
121	
122	b) Pick a single option for device signal polarity, and document this choice
123	in the binding. The gpio-specifier should represent the polarity of the signal
124	(at the GPIO controller) assuming that the device is configured for this
125	particular signal polarity choice. If software chooses to program the device
126	to generate or receive a signal of the opposite polarity, software will be
127	responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
128	controller.
129	
130	2) gpio-controller nodes
131	------------------------
132	
133	Every GPIO controller node must contain both an empty "gpio-controller"
134	property, and a #gpio-cells integer property, which indicates the number of
135	cells in a gpio-specifier.
136	
137	Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
138	instance of a hardware IP core on a silicon die, usually exposed to the
139	programmer as a coherent range of I/O addresses. Usually each such bank is
140	exposed in the device tree as an individual gpio-controller node, reflecting
141	the fact that the hardware was synthesized by reusing the same IP block a
142	few times over.
143	
144	Optionally, a GPIO controller may have a "ngpios" property. This property
145	indicates the number of in-use slots of available slots for GPIOs. The
146	typical example is something like this: the hardware register is 32 bits
147	wide, but only 18 of the bits have a physical counterpart. The driver is
148	generally written so that all 32 bits can be used, but the IP block is reused
149	in a lot of designs, some using all 32 bits, some using 18 and some using
150	12. In this case, setting "ngpios = <18>;" informs the driver that only the
151	first 18 GPIOs, at local offset 0 .. 17, are in use.
152	
153	If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
154	additional bitmask is needed to specify which GPIOs are actually in use,
155	and which are dummies. The bindings for this case has not yet been
156	specified, but should be specified if/when such hardware appears.
157	
158	Optionally, a GPIO controller may have a "gpio-line-names" property. This is
159	an array of strings defining the names of the GPIO lines going out of the
160	GPIO controller. This name should be the most meaningful producer name
161	for the system, such as a rail name indicating the usage. Package names
162	such as pin name are discouraged: such lines have opaque names (since they
163	are by definition generic purpose) and such names are usually not very
164	helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
165	reasonable line names as they describe what the line is used for. "GPIO0"
166	is not a good name to give to a GPIO line. Placeholders are discouraged:
167	rather use the "" (blank string) if the use of the GPIO line is undefined
168	in your design. The names are assigned starting from line offset 0 from
169	left to right from the passed array. An incomplete array (where the number
170	of passed named are less than ngpios) will still be used up until the last
171	provided valid line index.
172	
173	Example:
174	
175	gpio-controller@00000000 {
176		compatible = "foo";
177		reg = <0x00000000 0x1000>;
178		gpio-controller;
179		#gpio-cells = <2>;
180		ngpios = <18>;
181		gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
182			"LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
183			"Row A", "Row B", "Row C", "Row D", "NMI button",
184			"poweroff", "reset";
185	}
186	
187	The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
188	providing automatic GPIO request and configuration as part of the
189	gpio-controller's driver probe function.
190	
191	Each GPIO hog definition is represented as a child node of the GPIO controller.
192	Required properties:
193	- gpio-hog:   A property specifying that this child node represents a GPIO hog.
194	- gpios:      Store the GPIO information (id, flags, ...) for each GPIO to
195		      affect. Shall contain an integer multiple of the number of cells
196		      specified in its parent node (GPIO controller node).
197	Only one of the following properties scanned in the order shown below.
198	This means that when multiple properties are present they will be searched
199	in the order presented below and the first match is taken as the intended
200	configuration.
201	- input:      A property specifying to set the GPIO direction as input.
202	- output-low  A property specifying to set the GPIO direction as output with
203		      the value low.
204	- output-high A property specifying to set the GPIO direction as output with
205		      the value high.
206	
207	Optional properties:
208	- line-name:  The GPIO label name. If not present the node name is used.
209	
210	Example of two SOC GPIO banks defined as gpio-controller nodes:
211	
212		qe_pio_a: gpio-controller@1400 {
213			compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
214			reg = <0x1400 0x18>;
215			gpio-controller;
216			#gpio-cells = <2>;
217	
218			line_b {
219				gpio-hog;
220				gpios = <6 0>;
221				output-low;
222				line-name = "foo-bar-gpio";
223			};
224		};
225	
226		qe_pio_e: gpio-controller@1460 {
227			compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
228			reg = <0x1460 0x18>;
229			gpio-controller;
230			#gpio-cells = <2>;
231		};
232	
233	2.1) gpio- and pin-controller interaction
234	-----------------------------------------
235	
236	Some or all of the GPIOs provided by a GPIO controller may be routed to pins
237	on the package via a pin controller. This allows muxing those pins between
238	GPIO and other functions.
239	
240	It is useful to represent which GPIOs correspond to which pins on which pin
241	controllers. The gpio-ranges property described below represents this, and
242	contains information structures as follows:
243	
244		gpio-range-list ::= <single-gpio-range> [gpio-range-list]
245		single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>
246		numeric-gpio-range ::=
247				<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
248		named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
249		pinctrl-phandle : phandle to pin controller node
250		gpio-base : Base GPIO ID in the GPIO controller
251		pinctrl-base : Base pinctrl pin ID in the pin controller
252		count : The number of GPIOs/pins in this range
253	
254	The "pin controller node" mentioned above must conform to the bindings
255	described in ../pinctrl/pinctrl-bindings.txt.
256	
257	In case named gpio ranges are used (ranges with both <pinctrl-base> and
258	<count> set to 0), the property gpio-ranges-group-names contains one string
259	for every single-gpio-range in gpio-ranges:
260		gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]
261		gpiorange-name : Name of the pingroup associated to the GPIO range in
262				the respective pin controller.
263	
264	Elements of gpiorange-names-list corresponding to numeric ranges contain
265	the empty string. Elements of gpiorange-names-list corresponding to named
266	ranges contain the name of a pin group defined in the respective pin
267	controller. The number of pins/GPIOs in the range is the number of pins in
268	that pin group.
269	
270	Previous versions of this binding required all pin controller nodes that
271	were referenced by any gpio-ranges property to contain a property named
272	#gpio-range-cells with value <3>. This requirement is now deprecated.
273	However, that property may still exist in older device trees for
274	compatibility reasons, and would still be required even in new device
275	trees that need to be compatible with older software.
276	
277	Example 1:
278	
279		qe_pio_e: gpio-controller@1460 {
280			#gpio-cells = <2>;
281			compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
282			reg = <0x1460 0x18>;
283			gpio-controller;
284			gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
285		};
286	
287	Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
288	pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
289	pins 50..69.
290	
291	Example 2:
292	
293		gpio_pio_i: gpio-controller@14B0 {
294			#gpio-cells = <2>;
295			compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
296			reg = <0x1480 0x18>;
297			gpio-controller;
298			gpio-ranges =			<&pinctrl1 0 20 10>,
299							<&pinctrl2 10 0 0>,
300							<&pinctrl1 15 0 10>,
301							<&pinctrl2 25 0 0>;
302			gpio-ranges-group-names =	"",
303							"foo",
304							"",
305							"bar";
306		};
307	
308	Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
309	ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
310	are named "foo" and "bar".
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