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Documentation / devicetree / bindings / gpio / mrvl-gpio.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* Marvell PXA GPIO controller
2	
3	Required properties:
4	- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio",
5			"intel,pxa27x-gpio", "intel,pxa3xx-gpio",
6			"marvell,pxa93x-gpio", "marvell,mmp-gpio",
7			"marvell,mmp2-gpio" or marvell,pxa1928-gpio.
8	- reg : Address and length of the register set for the device
9	- interrupts : Should be the port interrupt shared by all gpio pins.
10	  There're three gpio interrupts in arch-pxa, and they're gpio0,
11	  gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
12	  gpio_mux.
13	- interrupt-names : Should be the names of irq resources. Each interrupt
14	  uses its own interrupt name, so there should be as many interrupt names
15	  as referenced interrupts.
16	- interrupt-controller : Identifies the node as an interrupt controller.
17	- #interrupt-cells: Specifies the number of cells needed to encode an
18	  interrupt source.
19	- gpio-controller : Marks the device node as a gpio controller.
20	- #gpio-cells : Should be two.  The first cell is the pin number and
21	  the second cell is used to specify flags. See gpio.txt for possible
22	  values.
23	
24	Example for a MMP platform:
25	
26		gpio: gpio@d4019000 {
27			compatible = "marvell,mmp-gpio";
28			reg = <0xd4019000 0x1000>;
29			interrupts = <49>;
30			interrupt-names = "gpio_mux";
31			gpio-controller;
32			#gpio-cells = <2>;
33			interrupt-controller;
34			#interrupt-cells = <1>;
35	      };
36	
37	Example for a PXA3xx platform:
38	
39		gpio: gpio@40e00000 {
40			compatible = "intel,pxa3xx-gpio";
41			reg = <0x40e00000 0x10000>;
42			interrupt-names = "gpio0", "gpio1", "gpio_mux";
43			interrupts = <8 9 10>;
44			gpio-controller;
45			#gpio-cells = <0x2>;
46			interrupt-controller;
47			#interrupt-cells = <0x2>;
48		};
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