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Documentation / devicetree / bindings / iommu / arm,smmu.txt




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Based on kernel version 4.9. Page generated on 2016-12-21 14:30 EST.

1	* ARM System MMU Architecture Implementation
2	
3	ARM SoCs may contain an implementation of the ARM System Memory
4	Management Unit Architecture, which can be used to provide 1 or 2 stages
5	of address translation to bus masters external to the CPU.
6	
7	The SMMU may also raise interrupts in response to various fault
8	conditions.
9	
10	** System MMU required properties:
11	
12	- compatible    : Should be one of:
13	
14	                        "arm,smmu-v1"
15	                        "arm,smmu-v2"
16	                        "arm,mmu-400"
17	                        "arm,mmu-401"
18	                        "arm,mmu-500"
19	                        "cavium,smmu-v2"
20	
21	                  depending on the particular implementation and/or the
22	                  version of the architecture implemented.
23	
24	- reg           : Base address and size of the SMMU.
25	
26	- #global-interrupts : The number of global interrupts exposed by the
27	                       device.
28	
29	- interrupts    : Interrupt list, with the first #global-irqs entries
30	                  corresponding to the global interrupts and any
31	                  following entries corresponding to context interrupts,
32	                  specified in order of their indexing by the SMMU.
33	
34	                  For SMMUv2 implementations, there must be exactly one
35	                  interrupt per context bank. In the case of a single,
36	                  combined interrupt, it must be listed multiple times.
37	
38	- #iommu-cells  : See Documentation/devicetree/bindings/iommu/iommu.txt
39	                  for details. With a value of 1, each "iommus" entry
40	                  represents a distinct stream ID emitted by that device
41	                  into the relevant SMMU.
42	
43	                  SMMUs with stream matching support and complex masters
44	                  may use a value of 2, where the second cell represents
45	                  an SMR mask to combine with the ID in the first cell.
46	                  Care must be taken to ensure the set of matched IDs
47	                  does not result in conflicts.
48	
49	** System MMU optional properties:
50	
51	- dma-coherent  : Present if page table walks made by the SMMU are
52	                  cache coherent with the CPU.
53	
54	                  NOTE: this only applies to the SMMU itself, not
55	                  masters connected upstream of the SMMU.
56	
57	- calxeda,smmu-secure-config-access : Enable proper handling of buggy
58	                  implementations that always use secure access to
59	                  SMMU configuration registers. In this case non-secure
60	                  aliases of secure registers have to be used during
61	                  SMMU configuration.
62	
63	** Deprecated properties:
64	
65	- mmu-masters (deprecated in favour of the generic "iommus" binding) :
66	                  A list of phandles to device nodes representing bus
67	                  masters for which the SMMU can provide a translation
68	                  and their corresponding Stream IDs. Each device node
69	                  linked from this list must have a "#stream-id-cells"
70	                  property, indicating the number of Stream ID
71	                  arguments associated with its phandle.
72	
73	** Examples:
74	
75	        /* SMMU with stream matching or stream indexing */
76	        smmu1: iommu {
77	                compatible = "arm,smmu-v1";
78	                reg = <0xba5e0000 0x10000>;
79	                #global-interrupts = <2>;
80	                interrupts = <0 32 4>,
81	                             <0 33 4>,
82	                             <0 34 4>, /* This is the first context interrupt */
83	                             <0 35 4>,
84	                             <0 36 4>,
85	                             <0 37 4>;
86	                #iommu-cells = <1>;
87	        };
88	
89	        /* device with two stream IDs, 0 and 7 */
90	        master1 {
91	                iommus = <&smmu1 0>,
92	                         <&smmu1 7>;
93	        };
94	
95	
96	        /* SMMU with stream matching */
97	        smmu2: iommu {
98	                ...
99	                #iommu-cells = <2>;
100	        };
101	
102	        /* device with stream IDs 0 and 7 */
103	        master2 {
104	                iommus = <&smmu2 0 0>,
105	                         <&smmu2 7 0>;
106	        };
107	
108	        /* device with stream IDs 1, 17, 33 and 49 */
109	        master3 {
110	                iommus = <&smmu2 1 0x30>;
111	        };
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