About Kernel Documentation Linux Kernel Contact Linux Resources Linux Blog

Documentation / devicetree / bindings / iommu / arm,smmu.txt




Custom Search

Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* ARM System MMU Architecture Implementation
2	
3	ARM SoCs may contain an implementation of the ARM System Memory
4	Management Unit Architecture, which can be used to provide 1 or 2 stages
5	of address translation to bus masters external to the CPU.
6	
7	The SMMU may also raise interrupts in response to various fault
8	conditions.
9	
10	** System MMU required properties:
11	
12	- compatible    : Should be one of:
13	
14	                        "arm,smmu-v1"
15	                        "arm,smmu-v2"
16	                        "arm,mmu-400"
17	                        "arm,mmu-401"
18	                        "arm,mmu-500"
19	                        "cavium,smmu-v2"
20	
21	                  depending on the particular implementation and/or the
22	                  version of the architecture implemented.
23	
24	- reg           : Base address and size of the SMMU.
25	
26	- #global-interrupts : The number of global interrupts exposed by the
27	                       device.
28	
29	- interrupts    : Interrupt list, with the first #global-irqs entries
30	                  corresponding to the global interrupts and any
31	                  following entries corresponding to context interrupts,
32	                  specified in order of their indexing by the SMMU.
33	
34	                  For SMMUv2 implementations, there must be exactly one
35	                  interrupt per context bank. In the case of a single,
36	                  combined interrupt, it must be listed multiple times.
37	
38	- #iommu-cells  : See Documentation/devicetree/bindings/iommu/iommu.txt
39	                  for details. With a value of 1, each IOMMU specifier
40	                  represents a distinct stream ID emitted by that device
41	                  into the relevant SMMU.
42	
43	                  SMMUs with stream matching support and complex masters
44	                  may use a value of 2, where the second cell of the
45	                  IOMMU specifier represents an SMR mask to combine with
46	                  the ID in the first cell.  Care must be taken to ensure
47	                  the set of matched IDs does not result in conflicts.
48	
49	** System MMU optional properties:
50	
51	- dma-coherent  : Present if page table walks made by the SMMU are
52	                  cache coherent with the CPU.
53	
54	                  NOTE: this only applies to the SMMU itself, not
55	                  masters connected upstream of the SMMU.
56	
57	- calxeda,smmu-secure-config-access : Enable proper handling of buggy
58	                  implementations that always use secure access to
59	                  SMMU configuration registers. In this case non-secure
60	                  aliases of secure registers have to be used during
61	                  SMMU configuration.
62	
63	- stream-match-mask : For SMMUs supporting stream matching and using
64	                  #iommu-cells = <1>, specifies a mask of bits to ignore
65			  when matching stream IDs (e.g. this may be programmed
66			  into the SMRn.MASK field of every stream match register
67			  used). For cases where it is desirable to ignore some
68	                  portion of every Stream ID (e.g. for certain MMU-500
69	                  configurations given globally unique input IDs). This
70	                  property is not valid for SMMUs using stream indexing,
71	                  or using stream matching with #iommu-cells = <2>, and
72	                  may be ignored if present in such cases.
73	
74	** Deprecated properties:
75	
76	- mmu-masters (deprecated in favour of the generic "iommus" binding) :
77	                  A list of phandles to device nodes representing bus
78	                  masters for which the SMMU can provide a translation
79	                  and their corresponding Stream IDs. Each device node
80	                  linked from this list must have a "#stream-id-cells"
81	                  property, indicating the number of Stream ID
82	                  arguments associated with its phandle.
83	
84	** Examples:
85	
86	        /* SMMU with stream matching or stream indexing */
87	        smmu1: iommu {
88	                compatible = "arm,smmu-v1";
89	                reg = <0xba5e0000 0x10000>;
90	                #global-interrupts = <2>;
91	                interrupts = <0 32 4>,
92	                             <0 33 4>,
93	                             <0 34 4>, /* This is the first context interrupt */
94	                             <0 35 4>,
95	                             <0 36 4>,
96	                             <0 37 4>;
97	                #iommu-cells = <1>;
98	        };
99	
100	        /* device with two stream IDs, 0 and 7 */
101	        master1 {
102	                iommus = <&smmu1 0>,
103	                         <&smmu1 7>;
104	        };
105	
106	
107	        /* SMMU with stream matching */
108	        smmu2: iommu {
109	                ...
110	                #iommu-cells = <2>;
111	        };
112	
113	        /* device with stream IDs 0 and 7 */
114	        master2 {
115	                iommus = <&smmu2 0 0>,
116	                         <&smmu2 7 0>;
117	        };
118	
119	        /* device with stream IDs 1, 17, 33 and 49 */
120	        master3 {
121	                iommus = <&smmu2 1 0x30>;
122	        };
123	
124	
125	        /* ARM MMU-500 with 10-bit stream ID input configuration */
126	        smmu3: iommu {
127	                compatible = "arm,mmu-500", "arm,smmu-v2";
128	                ...
129	                #iommu-cells = <1>;
130	                /* always ignore appended 5-bit TBU number */
131	                stream-match-mask = 0x7c00;
132	        };
133	
134	        bus {
135	                /* bus whose child devices emit one unique 10-bit stream
136	                   ID each, but may master through multiple SMMU TBUs */
137	                iommu-map = <0 &smmu3 0 0x400>;
138	                ...
139	        };
Hide Line Numbers
About Kernel Documentation Linux Kernel Contact Linux Resources Linux Blog

Information is copyright its respective author. All material is available from the Linux Kernel Source distributed under a GPL License. This page is provided as a free service by mjmwired.net.