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Documentation / devicetree / bindings / media / s5p-mfc.txt




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Based on kernel version 4.9. Page generated on 2016-12-21 14:30 EST.

1	* Samsung Multi Format Codec (MFC)
2	
3	Multi Format Codec (MFC) is the IP present in Samsung SoCs which
4	supports high resolution decoding and encoding functionalities.
5	The MFC device driver is a v4l2 driver which can encode/decode
6	video raw/elementary streams and has support for all popular
7	video codecs.
8	
9	Required properties:
10	  - compatible : value should be either one among the following
11		(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
12		(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
13		(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
14		(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
15	
16	  - reg : Physical base address of the IP registers and length of memory
17		  mapped region.
18	
19	  - interrupts : MFC interrupt number to the CPU.
20	  - clocks : from common clock binding: handle to mfc clock.
21	  - clock-names : from common clock binding: must contain "mfc",
22			  corresponding to entry in the clocks property.
23	
24	Optional properties:
25	  - power-domains : power-domain property defined with a phandle
26				   to respective power domain.
27	  - memory-region : from reserved memory binding: phandles to two reserved
28		memory regions, first is for "left" mfc memory bus interfaces,
29		second if for the "right" mfc memory bus, used when no SYSMMU
30		support is available
31	
32	Obsolete properties:
33	  - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
34		property instead
35	
36	
37	Example:
38	SoC specific DT entry:
39	
40	mfc: codec@13400000 {
41		compatible = "samsung,mfc-v5";
42		reg = <0x13400000 0x10000>;
43		interrupts = <0 94 0>;
44		power-domains = <&pd_mfc>;
45		clocks = <&clock 273>;
46		clock-names = "mfc";
47	};
48	
49	Reserved memory specific DT entry for given board (see reserved memory binding
50	for more information):
51	
52	reserved-memory {
53		#address-cells = <1>;
54		#size-cells = <1>;
55		ranges;
56	
57		mfc_left: region@51000000 {
58			compatible = "shared-dma-pool";
59			no-map;
60			reg = <0x51000000 0x800000>;
61		};
62	
63		mfc_right: region@43000000 {
64			compatible = "shared-dma-pool";
65			no-map;
66			reg = <0x43000000 0x800000>;
67		};
68	};
69	
70	Board specific DT entry:
71	
72	codec@13400000 {
73		memory-region = <&mfc_left>, <&mfc_right>;
74	};
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