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Documentation / devicetree / bindings / mmc / sdhci-msm.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* Qualcomm SDHCI controller (sdhci-msm)
2	
3	This file documents differences between the core properties in mmc.txt
4	and the properties used by the sdhci-msm driver.
5	
6	Required properties:
7	- compatible: Should contain "qcom,sdhci-msm-v4".
8	- reg: Base address and length of the register in the following order:
9		- Host controller register map (required)
10		- SD Core register map (required)
11	- interrupts: Should contain an interrupt-specifiers for the interrupts:
12		- Host controller interrupt (required)
13	- pinctrl-names: Should contain only one value - "default".
14	- pinctrl-0: Should specify pin control groups used for this controller.
15	- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
16	- clock-names: Should contain the following:
17		"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
18		"core"	- SDC MMC clock (MCLK) (required)
19		"bus"	- SDCC bus voter clock (optional)
20		"xo"	- TCXO clock (optional)
21	
22	Example:
23	
24		sdhc_1: sdhci@f9824900 {
25			compatible = "qcom,sdhci-msm-v4";
26			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
27			interrupts = <0 123 0>;
28			bus-width = <8>;
29			non-removable;
30	
31			vmmc-supply = <&pm8941_l20>;
32			vqmmc-supply = <&pm8941_s3>;
33	
34			pinctrl-names = "default";
35			pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
36	
37			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
38			clock-names = "core", "iface";
39		};
40	
41		sdhc_2: sdhci@f98a4900 {
42			compatible = "qcom,sdhci-msm-v4";
43			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
44			interrupts = <0 125 0>;
45			bus-width = <4>;
46			cd-gpios = <&msmgpio 62 0x1>;
47	
48			vmmc-supply = <&pm8941_l21>;
49			vqmmc-supply = <&pm8941_l13>;
50	
51			pinctrl-names = "default";
52			pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
53	
54			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
55			clock-names = "core", "iface";
56		};
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