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Documentation / devicetree / bindings / mtd / nand.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* NAND chip and NAND controller generic binding
2	
3	NAND controller/NAND chip representation:
4	
5	The NAND controller should be represented with its own DT node, and all
6	NAND chips attached to this controller should be defined as children nodes
7	of the NAND controller. This representation should be enforced even for
8	simple controllers supporting only one chip.
9	
10	Mandatory NAND controller properties:
11	- #address-cells: depends on your controller. Should at least be 1 to
12			  encode the CS line id.
13	- #size-cells: depends on your controller. Put zero unless you need a
14		       mapping between CS lines and dedicated memory regions
15	
16	Optional NAND controller properties
17	- ranges: only needed if you need to define a mapping between CS lines and
18		  memory regions
19	
20	Optional NAND chip properties:
21	
22	- nand-ecc-mode : String, operation mode of the NAND ecc mode.
23			  Supported values are: "none", "soft", "hw", "hw_syndrome",
24			  "hw_oob_first", "on-die".
25			  Deprecated values:
26			  "soft_bch": use "soft" and nand-ecc-algo instead
27	- nand-ecc-algo: string, algorithm of NAND ECC.
28			 Supported values are: "hamming", "bch".
29	- nand-bus-width : 8 or 16 bus width if not present 8
30	- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
31	
32	- nand-ecc-strength: integer representing the number of bits to correct
33			     per ECC step.
34	
35	- nand-ecc-step-size: integer representing the number of data bytes
36			      that are covered by a single ECC step.
37	
38	- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
39			     strength. The maximum ECC strength is both controller and
40			     chip dependent. The controller side has to select the ECC
41			     config providing the best strength and taking the OOB area
42			     size constraint into account.
43			     This is particularly useful when only the in-band area is
44			     used by the upper layers, and you want to make your NAND
45			     as reliable as possible.
46	
47	The ECC strength and ECC step size properties define the correction capability
48	of a controller. Together, they say a controller can correct "{strength} bit
49	errors per {size} bytes".
50	
51	The interpretation of these parameters is implementation-defined, so not all
52	implementations must support all possible combinations. However, implementations
53	are encouraged to further specify the value(s) they support.
54	
55	Example:
56	
57		nand-controller {
58			#address-cells = <1>;
59			#size-cells = <0>;
60	
61			/* controller specific properties */
62	
63			nand@0 {
64				reg = <0>;
65				nand-ecc-mode = "soft";
66				nand-ecc-algo = "bch";
67	
68				/* controller specific properties */
69			};
70		};
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