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Documentation / devicetree / bindings / mtd / stm32-quadspi.txt


Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.

1	* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI)
2	
3	Required properties:
4	- compatible: should be "st,stm32f469-qspi"
5	- reg: the first contains the register location and length.
6	       the second contains the memory mapping address and length
7	- reg-names: should contain the reg names "qspi" "qspi_mm"
8	- interrupts: should contain the interrupt for the device
9	- clocks: the phandle of the clock needed by the QSPI controller
10	- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
11	
12	Optional properties:
13	- resets: must contain the phandle to the reset controller.
14	
15	A spi flash must be a child of the nor_flash node and could have some
16	properties. Also see jedec,spi-nor.txt.
17	
18	Required properties:
19	- reg: chip-Select number (QSPI controller may connect 2 nor flashes)
20	- spi-max-frequency: max frequency of spi bus
21	
22	Optional property:
23	- spi-rx-bus-width: see ../spi/spi-bus.txt for the description
24	
25	Example:
26	
27	qspi: spi@a0001000 {
28		compatible = "st,stm32f469-qspi";
29		reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
30		reg-names = "qspi", "qspi_mm";
31		interrupts = <91>;
32		resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
33		clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
34		pinctrl-names = "default";
35		pinctrl-0 = <&pinctrl_qspi0>;
36	
37		flash@0 {
38			reg = <0>;
39			spi-rx-bus-width = <4>;
40			spi-max-frequency = <108000000>;
41			...
42		};
43	};
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