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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	Distributed Switch Architecture Device Tree Bindings
2	----------------------------------------------------
3	
4	Two bindings exist, one of which has been deprecated due to
5	limitations.
6	
7	Current Binding
8	---------------
9	
10	Switches are true Linux devices and can be probes by any means. Once
11	probed, they register to the DSA framework, passing a node
12	pointer. This node is expected to fulfil the following binding, and
13	may contain additional properties as required by the device it is
14	embedded within.
15	
16	Required properties:
17	
18	- ports		: A container for child nodes representing switch ports.
19	
20	Optional properties:
21	
22	- dsa,member	: A two element list indicates which DSA cluster, and position
23			  within the cluster a switch takes. <0 0> is cluster 0,
24			  switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1,
25			  switch 0. A switch not part of any cluster (single device
26			  hanging off a CPU port) must not specify this property
27	
28	The ports container has the following properties
29	
30	Required properties:
31	
32	- #address-cells	: Must be 1
33	- #size-cells		: Must be 0
34	
35	Each port children node must have the following mandatory properties:
36	- reg			: Describes the port address in the switch
37	
38	An uplink/downlink port between switches in the cluster has the following
39	mandatory property:
40	
41	- link			: Should be a list of phandles to other switch's DSA
42				  port. This port is used as the outgoing port
43				  towards the phandle ports. The full routing
44				  information must be given, not just the one hop
45				  routes to neighbouring switches.
46	
47	A CPU port has the following mandatory property:
48	
49	- ethernet		: Should be a phandle to a valid Ethernet device node.
50	                          This host device is what the switch port is
51				  connected to.
52	
53	A user port has the following optional property:
54	
55	- label			: Describes the label associated with this port, which
56	                          will become the netdev name.
57	
58	Port child nodes may also contain the following optional standardised
59	properties, described in binding documents:
60	
61	- phy-handle		: Phandle to a PHY on an MDIO bus. See
62				  Documentation/devicetree/bindings/net/ethernet.txt
63				  for details.
64	
65	- phy-mode		: See
66				  Documentation/devicetree/bindings/net/ethernet.txt
67				  for details.
68	
69	- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
70				  managed entity. See
71				  Documentation/devicetree/bindings/net/fixed-link.txt
72				  for details.
73	
74	Example
75	
76	The following example shows three switches on three MDIO busses,
77	linked into one DSA cluster.
78	
79	&mdio1 {
80		#address-cells = <1>;
81		#size-cells = <0>;
82	
83		switch0: switch0@0 {
84			compatible = "marvell,mv88e6085";
85			#address-cells = <1>;
86			#size-cells = <0>;
87			reg = <0>;
88	
89			dsa,member = <0 0>;
90	
91			ports {
92				#address-cells = <1>;
93				#size-cells = <0>;
94				port@0 {
95					reg = <0>;
96					label = "lan0";
97				};
98	
99				port@1 {
100					reg = <1>;
101					label = "lan1";
102				};
103	
104				port@2 {
105					reg = <2>;
106					label = "lan2";
107				};
108	
109				switch0port5: port@5 {
110					reg = <5>;
111					phy-mode = "rgmii-txid";
112					link = <&switch1port6
113						&switch2port9>;
114					fixed-link {
115						speed = <1000>;
116						full-duplex;
117					};
118				};
119	
120				port@6 {
121					reg = <6>;
122					ethernet = <&fec1>;
123					fixed-link {
124						speed = <100>;
125						full-duplex;
126					};
127				};
128			};
129		};
130	};
131	
132	&mdio2 {
133		#address-cells = <1>;
134		#size-cells = <0>;
135	
136		switch1: switch1@0 {
137			compatible = "marvell,mv88e6085";
138			#address-cells = <1>;
139			#size-cells = <0>;
140			reg = <0>;
141	
142			dsa,member = <0 1>;
143	
144			ports {
145				#address-cells = <1>;
146				#size-cells = <0>;
147				port@0 {
148					reg = <0>;
149					label = "lan3";
150					phy-handle = <&switch1phy0>;
151				};
152	
153				port@1 {
154					reg = <1>;
155					label = "lan4";
156					phy-handle = <&switch1phy1>;
157				};
158	
159				port@2 {
160					reg = <2>;
161					label = "lan5";
162					phy-handle = <&switch1phy2>;
163				};
164	
165				switch1port5: port@5 {
166					reg = <5>;
167					link = <&switch2port9>;
168					phy-mode = "rgmii-txid";
169					fixed-link {
170						speed = <1000>;
171						full-duplex;
172					};
173				};
174	
175				switch1port6: port@6 {
176					reg = <6>;
177					phy-mode = "rgmii-txid";
178					link = <&switch0port5>;
179					fixed-link {
180						speed = <1000>;
181						full-duplex;
182					};
183				};
184			};
185			mdio-bus {
186				#address-cells = <1>;
187				#size-cells = <0>;
188				switch1phy0: switch1phy0@0 {
189					reg = <0>;
190				};
191				switch1phy1: switch1phy0@1 {
192					reg = <1>;
193				};
194				switch1phy2: switch1phy0@2 {
195					reg = <2>;
196				};
197			};
198		 };
199	};
200	
201	&mdio4 {
202		#address-cells = <1>;
203		#size-cells = <0>;
204	
205		switch2: switch2@0 {
206			compatible = "marvell,mv88e6085";
207			#address-cells = <1>;
208			#size-cells = <0>;
209			reg = <0>;
210	
211			dsa,member = <0 2>;
212	
213			ports {
214				#address-cells = <1>;
215				#size-cells = <0>;
216				port@0 {
217					reg = <0>;
218					label = "lan6";
219				};
220	
221				port@1 {
222					reg = <1>;
223					label = "lan7";
224				};
225	
226				port@2 {
227					reg = <2>;
228					label = "lan8";
229				};
230	
231				port@3 {
232					reg = <3>;
233					label = "optical3";
234					fixed-link {
235						speed = <1000>;
236						full-duplex;
237						link-gpios = <&gpio6 2
238						      GPIO_ACTIVE_HIGH>;
239					};
240				};
241	
242				port@4 {
243					reg = <4>;
244					label = "optical4";
245					fixed-link {
246						speed = <1000>;
247						full-duplex;
248						link-gpios = <&gpio6 3
249						      GPIO_ACTIVE_HIGH>;
250					};
251				};
252	
253				switch2port9: port@9 {
254					reg = <9>;
255					phy-mode = "rgmii-txid";
256					link = <&switch1port5
257						&switch0port5>;
258					fixed-link {
259						speed = <1000>;
260						full-duplex;
261					};
262				};
263			};
264		};
265	};
266	
267	Deprecated Binding
268	------------------
269	
270	The deprecated binding makes use of a platform device to represent the
271	switches. The switches themselves are not Linux devices, and make use
272	of an MDIO bus for management.
273	
274	Required properties:
275	- compatible		: Should be "marvell,dsa"
276	- #address-cells	: Must be 2, first cell is the address on the MDIO bus
277				  and second cell is the address in the switch tree.
278				  Second cell is used only when cascading/chaining.
279	- #size-cells		: Must be 0
280	- dsa,ethernet		: Should be a phandle to a valid Ethernet device node
281	- dsa,mii-bus		: Should be a phandle to a valid MDIO bus device node
282	
283	Optional properties:
284	- interrupts		: property with a value describing the switch
285				  interrupt number (not supported by the driver)
286	
287	A DSA node can contain multiple switch chips which are therefore child nodes of
288	the parent DSA node. The maximum number of allowed child nodes is 4
289	(DSA_MAX_SWITCHES).
290	Each of these switch child nodes should have the following required properties:
291	
292	- reg			: Contains two fields. The first one describes the
293				  address on the MII bus. The second is the switch
294				  number that must be unique in cascaded configurations
295	- #address-cells	: Must be 1
296	- #size-cells		: Must be 0
297	
298	A switch child node has the following optional property:
299	
300	- eeprom-length		: Set to the length of an EEPROM connected to the
301				  switch. Must be set if the switch can not detect
302				  the presence and/or size of a connected EEPROM,
303				  otherwise optional.
304	
305	A switch may have multiple "port" children nodes
306	
307	Each port children node must have the following mandatory properties:
308	- reg			: Describes the port address in the switch
309	- label			: Describes the label associated with this port, special
310				  labels are "cpu" to indicate a CPU port and "dsa" to
311				  indicate an uplink/downlink port.
312	
313	Note that a port labelled "dsa" will imply checking for the uplink phandle
314	described below.
315	
316	Optional property:
317	- link			: Should be a list of phandles to another switch's DSA port.
318				  This property is only used when switches are being
319				  chained/cascaded together. This port is used as outgoing port
320				  towards the phandle port, which can be more than one hop away.
321	
322	- phy-handle		: Phandle to a PHY on an external MDIO bus, not the
323				  switch internal one. See
324				  Documentation/devicetree/bindings/net/ethernet.txt
325				  for details.
326	
327	- phy-mode		: String representing the connection to the designated
328				  PHY node specified by the 'phy-handle' property. See
329				  Documentation/devicetree/bindings/net/ethernet.txt
330				  for details.
331	
332	- mii-bus		: Should be a phandle to a valid MDIO bus device node.
333				  This mii-bus will be used in preference to the
334				  global dsa,mii-bus defined above, for this switch.
335	
336	Optional subnodes:
337	- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
338				  managed entity. See
339				  Documentation/devicetree/bindings/net/fixed-link.txt
340				  for details.
341	
342	Example:
343	
344		dsa@0 {
345			compatible = "marvell,dsa";
346			#address-cells = <2>;
347			#size-cells = <0>;
348	
349			interrupts = <10>;
350			dsa,ethernet = <&ethernet0>;
351			dsa,mii-bus = <&mii_bus0>;
352	
353			switch@0 {
354				#address-cells = <1>;
355				#size-cells = <0>;
356				reg = <16 0>;	/* MDIO address 16, switch 0 in tree */
357	
358				port@0 {
359					reg = <0>;
360					label = "lan1";
361					phy-handle = <&phy0>;
362				};
363	
364				port@1 {
365					reg = <1>;
366					label = "lan2";
367				};
368	
369				port@5 {
370					reg = <5>;
371					label = "cpu";
372				};
373	
374				switch0port6: port@6 {
375					reg = <6>;
376					label = "dsa";
377					link = <&switch1port0
378					        &switch2port0>;
379				};
380			};
381	
382			switch@1 {
383				#address-cells = <1>;
384				#size-cells = <0>;
385				reg = <17 1>;	/* MDIO address 17, switch 1 in tree */
386				mii-bus = <&mii_bus1>;
387				reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
388	
389				switch1port0: port@0 {
390					reg = <0>;
391					label = "dsa";
392					link = <&switch0port6>;
393				};
394				switch1port1: port@1 {
395					reg = <1>;
396					label = "dsa";
397					link = <&switch2port1>;
398				};
399			};
400	
401			switch@2 {
402				#address-cells = <1>;
403				#size-cells = <0>;
404				reg = <18 2>;	/* MDIO address 18, switch 2 in tree */
405				mii-bus = <&mii_bus1>;
406	
407				switch2port0: port@0 {
408					reg = <0>;
409					label = "dsa";
410					link = <&switch1port1
411					        &switch0port6>;
412				};
413			};
414		};
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