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Documentation / devicetree / bindings / pci / designware-pcie.txt




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Based on kernel version 4.8. Page generated on 2016-10-06 23:13 EST.

1	* Synopsys Designware PCIe interface
2	
3	Required properties:
4	- compatible: should contain "snps,dw-pcie" to identify the core.
5	- reg: Should contain the configuration address space.
6	- reg-names: Must be "config" for the PCIe configuration space.
7	    (The old way of getting the configuration address space from "ranges"
8	    is deprecated and should be avoided.)
9	- #address-cells: set to <3>
10	- #size-cells: set to <2>
11	- device_type: set to "pci"
12	- ranges: ranges for the PCI memory and I/O regions
13	- #interrupt-cells: set to <1>
14	- interrupt-map-mask and interrupt-map: standard PCI properties
15		to define the mapping of the PCIe interface to interrupt
16		numbers.
17	- num-lanes: number of lanes to use
18	
19	Optional properties:
20	- num-lanes: number of lanes to use (this property should be specified unless
21	  the link is brought already up in BIOS)
22	- reset-gpio: gpio pin number of power good signal
23	- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
24	  specify this property, to keep backwards compatibility a range of 0x00-0xff
25	  is assumed if not present)
26	- clocks: Must contain an entry for each entry in clock-names.
27		See ../clocks/clock-bindings.txt for details.
28	- clock-names: Must include the following entries:
29		- "pcie"
30		- "pcie_bus"
31	
32	Example configuration:
33	
34		pcie: pcie@dffff000 {
35			compatible = "snps,dw-pcie";
36			reg = <0xdffff000 0x1000>, /* Controller registers */
37			      <0xd0000000 0x2000>; /* PCI config space */
38			reg-names = "ctrlreg", "config";
39			#address-cells = <3>;
40			#size-cells = <2>;
41			device_type = "pci";
42			ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
43				  0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
44			interrupts = <25>, <24>;
45			#interrupt-cells = <1>;
46			num-lanes = <1>;
47		};
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