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Documentation / devicetree / bindings / pci / nvidia,tegra20-pcie.txt




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Based on kernel version 4.8. Page generated on 2016-10-06 23:13 EST.

1	NVIDIA Tegra PCIe controller
2	
3	Required properties:
4	- compatible: For Tegra20, must contain "nvidia,tegra20-pcie".  For Tegra30,
5	  "nvidia,tegra30-pcie".  For Tegra124, must contain "nvidia,tegra124-pcie".
6	  Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
7	  <chip> is tegra132 or tegra210.
8	- device_type: Must be "pci"
9	- reg: A list of physical base address and length for each set of controller
10	  registers. Must contain an entry for each entry in the reg-names property.
11	- reg-names: Must include the following entries:
12	  "pads": PADS registers
13	  "afi": AFI registers
14	  "cs": configuration space region
15	- interrupts: A list of interrupt outputs of the controller. Must contain an
16	  entry for each entry in the interrupt-names property.
17	- interrupt-names: Must include the following entries:
18	  "intr": The Tegra interrupt that is asserted for controller interrupts
19	  "msi": The Tegra interrupt that is asserted when an MSI is received
20	- bus-range: Range of bus numbers associated with this controller
21	- #address-cells: Address representation for root ports (must be 3)
22	  - cell 0 specifies the bus and device numbers of the root port:
23	    [23:16]: bus number
24	    [15:11]: device number
25	  - cell 1 denotes the upper 32 address bits and should be 0
26	  - cell 2 contains the lower 32 address bits and is used to translate to the
27	    CPU address space
28	- #size-cells: Size representation for root ports (must be 2)
29	- ranges: Describes the translation of addresses for root ports and standard
30	  PCI regions. The entries must be 6 cells each, where the first three cells
31	  correspond to the address as described for the #address-cells property
32	  above, the fourth cell is the physical CPU address to translate to and the
33	  fifth and six cells are as described for the #size-cells property above.
34	  - The first two entries are expected to translate the addresses for the root
35	    port registers, which are referenced by the assigned-addresses property of
36	    the root port nodes (see below).
37	  - The remaining entries setup the mapping for the standard I/O, memory and
38	    prefetchable PCI regions. The first cell determines the type of region
39	    that is setup:
40	    - 0x81000000: I/O memory region
41	    - 0x82000000: non-prefetchable memory region
42	    - 0xc2000000: prefetchable memory region
43	  Please refer to the standard PCI bus binding document for a more detailed
44	  explanation.
45	- #interrupt-cells: Size representation for interrupts (must be 1)
46	- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
47	  Please refer to the standard PCI bus binding document for a more detailed
48	  explanation.
49	- clocks: Must contain an entry for each entry in clock-names.
50	  See ../clocks/clock-bindings.txt for details.
51	- clock-names: Must include the following entries:
52	  - pex
53	  - afi
54	  - pll_e
55	  - cml (not required for Tegra20)
56	- resets: Must contain an entry for each entry in reset-names.
57	  See ../reset/reset.txt for details.
58	- reset-names: Must include the following entries:
59	  - pex
60	  - afi
61	  - pcie_x
62	
63	Required properties on Tegra124 and later (deprecated):
64	- phys: Must contain an entry for each entry in phy-names.
65	- phy-names: Must include the following entries:
66	  - pcie
67	
68	These properties are deprecated in favour of per-lane PHYs define in each of
69	the root ports (see below).
70	
71	Power supplies for Tegra20:
72	- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
73	- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
74	- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
75	  supply 1.05 V.
76	- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
77	  supply 1.05 V.
78	- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
79	
80	Power supplies for Tegra30:
81	- Required:
82	  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
83	    supply 1.05 V.
84	  - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
85	    supply 1.05 V.
86	  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
87	    supply 1.8 V.
88	  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
89	    Must supply 3.3 V.
90	- Optional:
91	  - If lanes 0 to 3 are used:
92	    - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
93	    - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
94	  - If lanes 4 or 5 are used:
95	    - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
96	    - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
97	
98	Power supplies for Tegra124:
99	- Required:
100	  - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
101	  - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
102	  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
103	    supply 1.05 V.
104	  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
105	    Must supply 3.3 V.
106	  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
107	    Must supply 3.3 V.
108	  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
109	    supply 2.8-3.3 V.
110	  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
111	    supply 1.05 V.
112	
113	Root ports are defined as subnodes of the PCIe controller node.
114	
115	Required properties:
116	- device_type: Must be "pci"
117	- assigned-addresses: Address and size of the port configuration registers
118	- reg: PCI bus address of the root port
119	- #address-cells: Must be 3
120	- #size-cells: Must be 2
121	- ranges: Sub-ranges distributed from the PCIe controller node. An empty
122	  property is sufficient.
123	- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
124	  are:
125	  - Root port 0 uses 4 lanes, root port 1 is unused.
126	  - Both root ports use 2 lanes.
127	
128	Required properties for Tegra124 and later:
129	- phys: Must contain an phandle to a PHY for each entry in phy-names.
130	- phy-names: Must include an entry for each active lane. Note that the number
131	  of entries does not have to (though usually will) be equal to the specified
132	  number of lanes in the nvidia,num-lanes property. Entries are of the form
133	  "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
134	
135	Examples:
136	=========
137	
138	Tegra20:
139	--------
140	
141	SoC DTSI:
142	
143		pcie-controller@80003000 {
144			compatible = "nvidia,tegra20-pcie";
145			device_type = "pci";
146			reg = <0x80003000 0x00000800   /* PADS registers */
147			       0x80003800 0x00000200   /* AFI registers */
148			       0x90000000 0x10000000>; /* configuration space */
149			reg-names = "pads", "afi", "cs";
150			interrupts = <0 98 0x04   /* controller interrupt */
151			              0 99 0x04>; /* MSI interrupt */
152			interrupt-names = "intr", "msi";
153	
154			#interrupt-cells = <1>;
155			interrupt-map-mask = <0 0 0 0>;
156			interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
157	
158			bus-range = <0x00 0xff>;
159			#address-cells = <3>;
160			#size-cells = <2>;
161	
162			ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
163				  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
164				  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
165				  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
166				  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
167	
168			clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
169			clock-names = "pex", "afi", "pll_e";
170			resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
171			reset-names = "pex", "afi", "pcie_x";
172			status = "disabled";
173	
174			pci@1,0 {
175				device_type = "pci";
176				assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
177				reg = <0x000800 0 0 0 0>;
178				status = "disabled";
179	
180				#address-cells = <3>;
181				#size-cells = <2>;
182	
183				ranges;
184	
185				nvidia,num-lanes = <2>;
186			};
187	
188			pci@2,0 {
189				device_type = "pci";
190				assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
191				reg = <0x001000 0 0 0 0>;
192				status = "disabled";
193	
194				#address-cells = <3>;
195				#size-cells = <2>;
196	
197				ranges;
198	
199				nvidia,num-lanes = <2>;
200			};
201		};
202	
203	Board DTS:
204	
205		pcie-controller@80003000 {
206			status = "okay";
207	
208			vdd-supply = <&pci_vdd_reg>;
209			pex-clk-supply = <&pci_clk_reg>;
210	
211			/* root port 00:01.0 */
212			pci@1,0 {
213				status = "okay";
214	
215				/* bridge 01:00.0 (optional) */
216				pci@0,0 {
217					reg = <0x010000 0 0 0 0>;
218	
219					#address-cells = <3>;
220					#size-cells = <2>;
221	
222					device_type = "pci";
223	
224					/* endpoint 02:00.0 */
225					pci@0,0 {
226						reg = <0x020000 0 0 0 0>;
227					};
228				};
229			};
230		};
231	
232	Note that devices on the PCI bus are dynamically discovered using PCI's bus
233	enumeration and therefore don't need corresponding device nodes in DT. However
234	if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
235	device nodes need to be added in order to allow the bus' children to be
236	instantiated at the proper location in the operating system's device tree (as
237	illustrated by the optional nodes in the example above).
238	
239	Tegra30:
240	--------
241	
242	SoC DTSI:
243	
244		pcie-controller@00003000 {
245			compatible = "nvidia,tegra30-pcie";
246			device_type = "pci";
247			reg = <0x00003000 0x00000800   /* PADS registers */
248			       0x00003800 0x00000200   /* AFI registers */
249			       0x10000000 0x10000000>; /* configuration space */
250			reg-names = "pads", "afi", "cs";
251			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
252				      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
253			interrupt-names = "intr", "msi";
254	
255			#interrupt-cells = <1>;
256			interrupt-map-mask = <0 0 0 0>;
257			interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
258	
259			bus-range = <0x00 0xff>;
260			#address-cells = <3>;
261			#size-cells = <2>;
262	
263			ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
264				  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
265				  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
266				  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
267				  0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
268				  0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
269	
270			clocks = <&tegra_car TEGRA30_CLK_PCIE>,
271				 <&tegra_car TEGRA30_CLK_AFI>,
272				 <&tegra_car TEGRA30_CLK_PLL_E>,
273				 <&tegra_car TEGRA30_CLK_CML0>;
274			clock-names = "pex", "afi", "pll_e", "cml";
275			resets = <&tegra_car 70>,
276				 <&tegra_car 72>,
277				 <&tegra_car 74>;
278			reset-names = "pex", "afi", "pcie_x";
279			status = "disabled";
280	
281			pci@1,0 {
282				device_type = "pci";
283				assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
284				reg = <0x000800 0 0 0 0>;
285				status = "disabled";
286	
287				#address-cells = <3>;
288				#size-cells = <2>;
289				ranges;
290	
291				nvidia,num-lanes = <2>;
292			};
293	
294			pci@2,0 {
295				device_type = "pci";
296				assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
297				reg = <0x001000 0 0 0 0>;
298				status = "disabled";
299	
300				#address-cells = <3>;
301				#size-cells = <2>;
302				ranges;
303	
304				nvidia,num-lanes = <2>;
305			};
306	
307			pci@3,0 {
308				device_type = "pci";
309				assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
310				reg = <0x001800 0 0 0 0>;
311				status = "disabled";
312	
313				#address-cells = <3>;
314				#size-cells = <2>;
315				ranges;
316	
317				nvidia,num-lanes = <2>;
318			};
319		};
320	
321	Board DTS:
322	
323		pcie-controller@00003000 {
324			status = "okay";
325	
326			avdd-pexa-supply = <&ldo1_reg>;
327			vdd-pexa-supply = <&ldo1_reg>;
328			avdd-pexb-supply = <&ldo1_reg>;
329			vdd-pexb-supply = <&ldo1_reg>;
330			avdd-pex-pll-supply = <&ldo1_reg>;
331			avdd-plle-supply = <&ldo1_reg>;
332			vddio-pex-ctl-supply = <&sys_3v3_reg>;
333			hvdd-pex-supply = <&sys_3v3_pexs_reg>;
334	
335			pci@1,0 {
336				status = "okay";
337			};
338	
339			pci@3,0 {
340				status = "okay";
341			};
342		};
343	
344	Tegra124:
345	---------
346	
347	SoC DTSI:
348	
349		pcie-controller@01003000 {
350			compatible = "nvidia,tegra124-pcie";
351			device_type = "pci";
352			reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
353			       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
354			       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
355			reg-names = "pads", "afi", "cs";
356			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
357				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
358			interrupt-names = "intr", "msi";
359	
360			#interrupt-cells = <1>;
361			interrupt-map-mask = <0 0 0 0>;
362			interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
363	
364			bus-range = <0x00 0xff>;
365			#address-cells = <3>;
366			#size-cells = <2>;
367	
368			ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
369				  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
370				  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
371				  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
372				  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
373	
374			clocks = <&tegra_car TEGRA124_CLK_PCIE>,
375				 <&tegra_car TEGRA124_CLK_AFI>,
376				 <&tegra_car TEGRA124_CLK_PLL_E>,
377				 <&tegra_car TEGRA124_CLK_CML0>;
378			clock-names = "pex", "afi", "pll_e", "cml";
379			resets = <&tegra_car 70>,
380				 <&tegra_car 72>,
381				 <&tegra_car 74>;
382			reset-names = "pex", "afi", "pcie_x";
383			status = "disabled";
384	
385			pci@1,0 {
386				device_type = "pci";
387				assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
388				reg = <0x000800 0 0 0 0>;
389				status = "disabled";
390	
391				#address-cells = <3>;
392				#size-cells = <2>;
393				ranges;
394	
395				nvidia,num-lanes = <2>;
396			};
397	
398			pci@2,0 {
399				device_type = "pci";
400				assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
401				reg = <0x001000 0 0 0 0>;
402				status = "disabled";
403	
404				#address-cells = <3>;
405				#size-cells = <2>;
406				ranges;
407	
408				nvidia,num-lanes = <1>;
409			};
410		};
411	
412	Board DTS:
413	
414		pcie-controller@01003000 {
415			status = "okay";
416	
417			avddio-pex-supply = <&vdd_1v05_run>;
418			dvddio-pex-supply = <&vdd_1v05_run>;
419			avdd-pex-pll-supply = <&vdd_1v05_run>;
420			hvdd-pex-supply = <&vdd_3v3_lp0>;
421			hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
422			vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
423			avdd-pll-erefe-supply = <&avdd_1v05_run>;
424	
425			/* Mini PCIe */
426			pci@1,0 {
427				phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
428				phy-names = "pcie-0";
429				status = "okay";
430			};
431	
432			/* Gigabit Ethernet */
433			pci@2,0 {
434				phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
435				phy-names = "pcie-0";
436				status = "okay";
437			};
438		};
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