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Documentation / devicetree / bindings / phy / samsung-phy.txt




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Based on kernel version 4.8. Page generated on 2016-10-06 23:13 EST.

1	Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY
2	-------------------------------------------------
3	
4	Required properties:
5	- compatible : should be one of the listed compatibles:
6		- "samsung,s5pv210-mipi-video-phy"
7		- "samsung,exynos5420-mipi-video-phy"
8		- "samsung,exynos5433-mipi-video-phy"
9	- #phy-cells : from the generic phy bindings, must be 1;
10	
11	In case of s5pv210 and exynos5420 compatible PHYs:
12	- syscon - phandle to the PMU system controller
13	
14	In case of exynos5433 compatible PHY:
15	 - samsung,pmu-syscon - phandle to the PMU system controller
16	 - samsung,disp-sysreg - phandle to the DISP system registers controller
17	 - samsung,cam0-sysreg - phandle to the CAM0 system registers controller
18	 - samsung,cam1-sysreg - phandle to the CAM1 system registers controller
19	
20	For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
21	the PHY specifier identifies the PHY and its meaning is as follows:
22	  0 - MIPI CSIS 0,
23	  1 - MIPI DSIM 0,
24	  2 - MIPI CSIS 1,
25	  3 - MIPI DSIM 1.
26	"samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
27	supports additional fifth PHY:
28	  4 - MIPI CSIS 2.
29	
30	Samsung EXYNOS SoC series Display Port PHY
31	-------------------------------------------------
32	
33	Required properties:
34	- compatible : should be one of the following supported values:
35		 - "samsung,exynos5250-dp-video-phy"
36		 - "samsung,exynos5420-dp-video-phy"
37	- samsung,pmu-syscon: phandle for PMU system controller interface, used to
38			      control pmu registers for power isolation.
39	- #phy-cells : from the generic PHY bindings, must be 0;
40	
41	Samsung S5P/EXYNOS SoC series USB PHY
42	-------------------------------------------------
43	
44	Required properties:
45	- compatible : should be one of the listed compatibles:
46		- "samsung,exynos3250-usb2-phy"
47		- "samsung,exynos4210-usb2-phy"
48		- "samsung,exynos4x12-usb2-phy"
49		- "samsung,exynos5250-usb2-phy"
50		- "samsung,s5pv210-usb2-phy"
51	- reg : a list of registers used by phy driver
52		- first and obligatory is the location of phy modules registers
53	- samsung,sysreg-phandle - handle to syscon used to control the system registers
54	- samsung,pmureg-phandle - handle to syscon used to control PMU registers
55	- #phy-cells : from the generic phy bindings, must be 1;
56	- clocks and clock-names:
57		- the "phy" clock is required by the phy module, used as a gate
58		- the "ref" clock is used to get the rate of the clock provided to the
59		  PHY module
60	
61	Optional properties:
62	- vbus-supply: power-supply phandle for vbus power source
63	
64	The first phandle argument in the PHY specifier identifies the PHY, its
65	meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
66	and Exynos 4212) it is as follows:
67	  0 - USB device ("device"),
68	  1 - USB host ("host"),
69	  2 - HSIC0 ("hsic0"),
70	  3 - HSIC1 ("hsic1"),
71	Exynos3250 has only USB device phy available as phy 0.
72	
73	Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
74	register is supplied.
75	
76	Example:
77	
78	For Exynos 4412 (compatible with Exynos 4212):
79	
80	usbphy: phy@125b0000 {
81		compatible = "samsung,exynos4x12-usb2-phy";
82		reg = <0x125b0000 0x100>;
83		clocks = <&clock 305>, <&clock 2>;
84		clock-names = "phy", "ref";
85		status = "okay";
86		#phy-cells = <1>;
87		samsung,sysreg-phandle = <&sys_reg>;
88		samsung,pmureg-phandle = <&pmu_reg>;
89	};
90	
91	Then the PHY can be used in other nodes such as:
92	
93	phy-consumer@12340000 {
94		phys = <&usbphy 2>;
95		phy-names = "phy";
96	};
97	
98	Refer to DT bindings documentation of particular PHY consumer devices for more
99	information about required PHYs and the way of specification.
100	
101	Samsung SATA PHY Controller
102	---------------------------
103	
104	SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
105	Each SATA PHY controller should have its own node.
106	
107	Required properties:
108	- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
109	- reg : offset and length of the SATA PHY register set;
110	- #phy-cells : must be zero
111	- clocks : must be exactly one entry
112	- clock-names : must be "sata_phyctrl"
113	- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
114	- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
115	
116	Example:
117		sata_phy: sata-phy@12170000 {
118			compatible = "samsung,exynos5250-sata-phy";
119			reg = <0x12170000 0x1ff>;
120			clocks = <&clock 287>;
121			clock-names = "sata_phyctrl";
122			#phy-cells = <0>;
123			samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
124			samsung,syscon-phandle = <&pmu_syscon>;
125		};
126	
127	Device-Tree bindings for sataphy i2c client driver
128	--------------------------------------------------
129	
130	Required properties:
131	compatible: Should be "samsung,exynos-sataphy-i2c"
132	- reg: I2C address of the sataphy i2c device.
133	
134	Example:
135	
136		sata_phy_i2c:sata-phy@38 {
137			compatible = "samsung,exynos-sataphy-i2c";
138			reg = <0x38>;
139		};
140	
141	Samsung Exynos5 SoC series USB DRD PHY controller
142	--------------------------------------------------
143	
144	Required properties:
145	- compatible : Should be set to one of the following supported values:
146		- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
147		- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
148		- "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.
149		- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
150	- reg : Register offset and length of USB DRD PHY register set;
151	- clocks: Clock IDs array as required by the controller
152	- clock-names: names of clocks correseponding to IDs in the clock property;
153		       Required clocks:
154		- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
155		       used for register access.
156		- ref: PHY's reference clock (usually crystal clock), used for
157		       PHY operations, associated by phy name. It is used to
158		       determine bit values for clock settings register.
159		       For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
160		- optional clocks: Exynos5433 & Exynos7 SoC has now following additional
161				   gate clocks available:
162				   - phy_pipe: for PIPE3 phy
163				   - phy_utmi: for UTMI+ phy
164				   - itp: for ITP generation
165	- samsung,pmu-syscon: phandle for PMU system controller interface, used to
166			      control pmu registers for power isolation.
167	- #phy-cells : from the generic PHY bindings, must be 1;
168	
169	For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
170	compatible PHYs, the second cell in the PHY specifier identifies the
171	PHY id, which is interpreted as follows:
172	  0 - UTMI+ type phy,
173	  1 - PIPE3 type phy,
174	
175	Example:
176		usbdrd_phy: usbphy@12100000 {
177			compatible = "samsung,exynos5250-usbdrd-phy";
178			reg = <0x12100000 0x100>;
179			clocks = <&clock 286>, <&clock 1>;
180			clock-names = "phy", "ref";
181			samsung,pmu-syscon = <&pmu_system_controller>;
182			#phy-cells = <1>;
183		};
184	
185	- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
186		   'usbdrd_phy' nodes should have numbered alias in the aliases node,
187		   in the form of usbdrdphyN, N = 0, 1... (depending on number of
188		   controllers).
189	Example:
190		aliases {
191			usbdrdphy0 = &usb3_phy0;
192			usbdrdphy1 = &usb3_phy1;
193		};
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